CYW134MOXCT Silicon Laboratories Inc, CYW134MOXCT Datasheet - Page 8

• Manufacturer Part Number: CYW134MOXCT
• Description: Clock Generators & Support Products DRCG Rambus refer to W134 datasheet
• Manufacturer: Silicon Laboratories Inc

Specifications of CYW134MOXCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 24, 2006
Absolute Maximum Conditions
External Component Values
Operating Conditions
Notes:
V
V
R
R
C
C
V
T
t
t
DC
FM
PM
t
t
DC
t
C
DC
C
V
V
V
V
V
V
V
V
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z
3. Do not populate C
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Refclk jitter measured at V
6. If input modulation is used: input modulation is allowed but not required.
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
CYCLE,IN
J,IN
CYCLE,PD
ERR,INIT
I,SR
A
DD, ABS
I, ABS
DD
IL
IH
IL,R
IH,R
IL,PD
IH,PD
DDIR
DDIPD
S
P
F
MID
IN,PD
IN,CMOS
Parameter
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
IN
IN
IN,PD
IN,PD
IN
Parameter
[6]
Parameter
Supply Voltage
Ambient Operating Temperature
Refclk Input Cycle Time
Input Cycle-to-Cycle Jitter
Input Duty Cycle over 10,000 Cycles
Input Frequency of Modulation
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
Phase Detector Input Cycle Time at PclkM & SynclkN
Initial Phase error at Phase Detector Inputs
Phase Detector Input Duty Cycle over 10,000 Cycles
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
SynclkN, and Refclk
Input Capacitance at PclkM, SynclkN, and Refclk
Input Capacitance matching at PclkM and SynclkN
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)
Input (CMOS) Signal Low Voltage
Input (CMOS) Signal High Voltage
Refclk input Low Voltage
Refclk input High Voltage
Input Signal Low Voltage for PD Inputs and StopB
Input Signal High Voltage for PD Inputs and StopB
Input Supply Reference for Refclk
Input Supply Reference for PD Inputs
F
. Leave pads for future use.
Max. voltage on V
Max. voltage on any pin with respect ground
DDIR
Serial Resistor
Parallel Resistor
Edge Rate Filter Capacitor
AC Ground Capacitor
[7]
(nom)/2.
[4]
[2]
DD
[1]
with respect to ground
[5]
Description
Description
Description
AC
< 100 mV.
[7]
[7]
CH
= 28Ω.
470 pF
4–15
3.135
1.235
1.235
Min.
–0.5
Min.
0.7
0.7
0.7
10
40
30
30
25
39
51
0
–
–
–
1
–
–
–
–
–
–
Min.
–0.5
–0.5
[3]
V
0.1 μF
3.465
3.465
2.625
0.5
±10%
Max.
Max.
DD
±5%
±5%
250
100
0.6
0.5
0.5
0.3
0.3
0.3
70
40
60
33
75
10
Max.
4
7
–
–
–
4.0
[8]
+ 0.5
Page 8 of 11
W134
t
t
%t
CYCLE,PD
CYCLE,PD
V
V
V
V
±20%
VDD
VDD
Unit
Unit
V/ns
DDIPD
DDIPD
kHz
CYCLE
Unit
DDIR
DDIR
pF
°C
pF
pF
pF
ns
ps
ns
%
%
Ω
Ω
V
V
V
V
V