CY28447LFXC Silicon Laboratories Inc, CY28447LFXC Datasheet
CY28447LFXC
Specifications of CY28447LFXC
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CY28447LFXC Summary of contents
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Features ® • Compliant to Intel CK410M • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 27 MHz Spread and Non-spread video clock • 48 MHz USB ...
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Pin Description Pin No. Name 1, 49, 54, 65 VDD_SRC 2, 3, 50, 51, SRCT/C[1:9] 52, 53, 55, 56, 58, 59, 60, 61, 63, 64, 66, 67, 69 VSS_SRC 5, 6 CPUT2_ITP/SRCT10, CPUC2_ITP/SRCC10 7 VDDA 8 VSSA ...
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Pin Description (continued) Pin No. Name 39 VTT_PWRGD#/PD 40 VDD_48 41 48M/FSA 42 VSS_48 43, 44 DOT96T/ 27M_NSS DOT96C/ 27M_SS 45 FSB/TEST_MODE 47, 48 SRC[T/C]0/ LCD100M[T/C] Frequency Select Pins (FSA, FSB, and FSC) Host clock frequency selection is achieved by ...
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Byte Count ...
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Control Registers Byte 0: Control Register 0 Bit @Pup Name 7 1 SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C]0 /LCD_96_100M[T/C] Byte 1: Control Register 1 ...
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Byte 3: Control Register 3 Bit @Pup Name 7 0 SRC7 6 0 SRC6 5 0 SRC5 4 0 SRC4 3 0 SRC3 2 0 SRC2 1 0 SRC1 0 0 SRC0 Byte 4: Control Register 4 Bit @Pup Name ...
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Byte 5: Control Register 5 (continued) Bit @Pup Name 1 0 CPU[T/C CPU[T/C]0 Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL 6 0 TEST_MODE 5 1 REF1 4 1 REF0 3 1 PCI, PCIF and ...
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Byte 9: Control Register 9 Bit @Pup Name 7 0 RESERVED 6 0 RESERVED RESERVED 2 1 27M_SS 1 1 27M_SS Spread Enable 27M_SS Spread spectrum enable RESERVED Byte 10: Control Register ...
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Byte 12: Control Register 12 Bit @Pup Name 7 0 CLKREQ CLKREQ CLKREQ CLKREQ CLKREQ CLKREQ CLKREQ CLKREQ#2 Byte 13: Control Register 13 Bit @Pup Name ...
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Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the ...
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PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous ...
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CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that ...
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CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs ...
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PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- tions to a HIGH level. PCI_STP# PCI_F PCI SRC ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...
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AC Electrical Specifications (continued) Parameter Description V Voltage High HIGH V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX V Maximum Overshoot Voltage OVS V Minimum Undershoot Voltage UDS V Ring Back Voltage RB SRC at 0.7V ...
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AC Electrical Specifications (continued) Parameter Description SSCT and SSCC Rise and Fall Time Rise/Fall Matching RFM ΔT Rise TimeVariation R ΔT Fall Time Variation F V Voltage High HIGH V Voltage Low LOW V ...
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AC Electrical Specifications (continued) Parameter Description T Period PERIOD T Absolute Period PERIODAbs T 48_M High time HIGH T 48_M Low time LOW Rising and Falling Edge Rate Cycle to Cycle Jitter CCJ L ...
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Test and Measurement Set-up For Single-ended Signals and Reference The following diagram shows test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB REF Figure 15.Single-ended Load Configuration Low Drive Option ...
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... Part Number Lead-free CY28447LFXC 72-pin QFN CY28447LFXCT 72-pin QFN – Tape and Reel Package Diagram While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...