MC100LVEP111FA ON Semiconductor, MC100LVEP111FA Datasheet
MC100LVEP111FA
Specifications of MC100LVEP111FA
Available stocks
Related parts for MC100LVEP111FA
MC100LVEP111FA Summary of contents
Page 1
MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either ...
Page 2
MC100LVEP111 Warning: All ...
Page 3
Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Charged Device Model Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. ...
Page 4
Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...
Page 5
Table 5. PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended) IH (Note 4) V Input LOW Voltage (Single−Ended) IL ...
Page 6
Table 7. NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 11 Output LOW Voltage (Note 11 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...
Page 7
Table 9. AC CHARACTERISTICS V Characteristic Symbol f Maximum Frequency (Figure 4) maxPECL/HSTL t Propagation Delay PLH t (Differential Configuration) PHL t Within−Device Skew (Note 15) skew Within−Device Skew @ 2.5 V (Note 15) Device−to−Device Skew (Note 16) t CLOCK ...
Page 8
MC100LVEP111 CLKx 50 W LVPECL V TT Driver 50 W CLK − 2 Figure 5. LVPECL ...
Page 9
V CC LVCMOS LVTTL Single−Ended Driver V EE Figure 9. Single−Ended Interface LVCMOS/LVTTL in Interface Using an External Voltage Reference V CC LVCMOS LVTTL Single−Ended Driver V EE Figure 10. Single−Ended Interface LVCMOS/LVTTL in Interface Using ...
Page 10
... Quadrant D = Lower Right Figure 12. Tape and Reel Pin 1 Quadrant Orientation ORDERING INFORMATION Device MC100LVEP111FA MC100LVEP111FAG MC100LVEP111FAR2 MC100LVEP111FARG M100LVEP111FATW M100LVEP111FATWG MC100LVEP111MNG MC100LVEP111MNRG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...
Page 11
Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
Page 12
−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 0.20 (0.008) AB T-U Z −U− ...
Page 13
... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81− ...