CY2PP326AI Cypress Semiconductor Corp, CY2PP326AI Datasheet

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CY2PP326AI

Manufacturer Part Number
CY2PP326AI
Description
Clock Drivers & Distribution 2.5V or 3.3V 1.5GHz IND
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY2PP326AI

Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Clock Inputs
2
Output Logic Level
ECL, PECL
Supply Voltage (max)
+/- 3.465 V
Supply Voltage (min)
+/- 2.375 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2PP326AI
Manufacturer:
CY
Quantity:
84
Cypress Semiconductor Corporation
Document #: 38-07506 Rev.*D
Features
• Six ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 250 ps device-to-device skew
• 950 ps propagation delay (typical)
• 1.2 GHz Operation
• 2.8 ps RMS period jitter (max.)
• PECL mode supply range: V
• ECL mode supply range: V
• Industrial temperature range: –40°C to 85°C
• 32-pin 1.4mm TQFP package
• Temperature compensation like 100K ECL
• Pin Compatible with MC100ES6254
CLK0#
CLK1#
O EA#
O EB#
CLK0
CLK1
SEL0
SEL1
with V
with V
Block Diagram
VCC
EE
EE
VEE
VEE
VEE
VCC
VEE
= 0V
= 0V
Sync
CC
EE
= 2.5V± 5% to 3.3V±5%
= –2.5V± 5% to –3.3V±5%
0
0
1
1
Bank A
B ank B
3901 North First Street
2 x 2 Clock and Data Switch Buffer
Functional Description
The CY2PP326 is a low-skew, low propagation delay 2 x 2
differential clock, data switch, and fanout buffer targeted to
meet the requirements of high-performance clock and data
distribution applications. The device is implemented on SiGe
technology and has a fully differential internal architecture that
is optimized to achieve low-signal skews at operating
frequencies of up to 1.5 GHz.
The device features two differential input paths which are mul-
tiplexed internally to six outputs grouped in two banks. The
muxes are controlled by SEL(0:1) control inputs. The
CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and
as a clock/data repeater or multiplexer.
Since the CY2PP326 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems and for switching data signals
between different channels. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP326 delivers consistent, guaranteed
performance over differing platforms.
QA0
QA0#
QA1
QA1#
QA2
QA2#
Q B0
Q B0#
Q B1
Q B1#
Q B2
Q B2#
Pin Configuration
CLK1#
OEB#
CLK1
San Jose
SEL1
VCC
VCC
VEE
VEE
4
5
6
7
8
1
2
3
32
9
,
CA 95134
10
31
CY2PP326
11
30
FastEdge™ Series
12
29
13
28
Revised July 28, 2004
14
27
15
26
16
CY2PP326
25
408-943-2600
21
20
19
18
17
24
23
22
VCC
VEE
OEA#
CLK0
CLK0#
SEL0
VEE
VCC

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CY2PP326AI Summary of contents

Page 1

... SEL1 VEE O EA# Sync O EB# VEE Cypress Semiconductor Corporation Document #: 38-07506 Rev.* Clock and Data Switch Buffer Functional Description The CY2PP326 is a low-skew, low propagation delay differential clock, data switch, and fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications ...

Page 2

Pin Definitions Pin Name 19,3 SEL0,SEL1 22,6 OEA#,OEB# 21,4 CLK(0:1) 20,5 CLK(0:1)# 31,28,25 QA(0:2) 32,29,26 QA(0:2)# 10,13,16 QB(0:2) 9,12,15 QB(0:2)# 2,7,18,23, VEE 1,8,11,14,17,24,27,30 VCC Table 1. Function Table Control Default OAE# 0 QA(0–2), QX(0–2)# are active. Deassertion of OE# can ...

Page 3

Absolute Maximum Ratings Parameter Description V Positive Supply Voltage CC V Negative Supply Voltage EE T Temperature, Storage S T Temperature, Junction J ESD ESD Protection h M Moisture Sensitivity Level SL Gate Count Total Number of Used Gates Multiple ...

Page 4

ECL DC Electrical Specifications Parameter Description V Negative Power Supply EE V Differential cross point voltage CMR V Output High Voltage OH V Output Low Voltage –3.3V ± –2.5V ± ...

Page 5

Timing Definitions VCC VIH VPP VIL VEE tr, tf, 20-80 ...

Page 6

CLKX CLKX 2 1 50% OEX tPDL(OE[X] to Q[X} Q[X] Q[X]# Test Configuration Standard test load using a differential pulse generator and differential measurement instrument ...

Page 7

... Figure 10. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other Ordering Information Part Number CY2PP326AI CY2PP326AIT Document #: 38-07506 Rev.* " " ...

Page 8

... Document #: 38-07506 Rev.*D © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 9

Document History Page Document Title: CY2PP326 FastEdge™ Series Clock and Data Switch Buffer Document Number: 38-07506 REV. ECN NO. Issue Date ** 122361 02/12/03 *A 129269 09/09/03 *B 131346 11/20/03 *C 237751 See ECN *D 247620 See ...

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