FIN1022MTC_Q Fairchild Semiconductor, FIN1022MTC_Q Datasheet
FIN1022MTC_Q
Specifications of FIN1022MTC_Q
Related parts for FIN1022MTC_Q
FIN1022MTC_Q Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation Features Low jitter, 800 Mbps full differential data path ...
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Connection Diagram Function Table Inputs SEL SEL ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Driver Short Circuit Current (I ) OSD Storage Temperature Range (T ) STG Max Junction Temperature ( Lead ...
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AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter t Differential Output Propagation Delay PLHD LOW-to-HIGH t Differential Output Propagation Delay PHLD HIGH-to-LOW t Differential Output Rise Time (20% to 80%) TLHD t Differential ...
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Required Specifications 1. When the true and complement LVDS outputs (having a 75 connected between outputs) are connected to 3.75 k resistors and the common point of those 3.75 k resistors are connected to a voltage source that sweeps from ...
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Required Specifications (Continued) FIGURE 3. LVDS Driver DC Test Circuit FIGURE 5. LVDS Input to LVDS Output AC Waveforms www.fairchildsemi.com Note A: All input pulses have frequency 50 MHz Note B: C includes all probe and jig capacitances ...
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Required Specifications (Continued) FIGURE 7. LVTTL Input to LVDS Output AC Waveforms FIGURE 9. Enable and Disable AC Waveforms Note A: All input pulses have frequency 10MHz Note B: C includes all probe and jig capacitances. ...
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Required Specifications (Continued) FIGURE 10. Set-up and Hold Time Specification www.fairchildsemi.com 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 9 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...