DS2174Q/T&R Maxim Integrated Products, DS2174Q/T&R Datasheet
DS2174Q/T&R
Specifications of DS2174Q/T&R
Related parts for DS2174Q/T&R
DS2174Q/T&R Summary of contents
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GENERAL DESCRIPTION The DS2174 enhanced bit error-rate tester (EBERT software-programmable test-pattern generator, receiver, and analyzer capable of meeting the most stringent error-performance requirements of digital transmission facilities. It features bit-serial, nibble-parallel, and byte- parallel data interfaces, and ...
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GENERAL OPERATION 1 ATTERN ENERATION 1.1.1 Polynomial Generation.......................................................................................... 4 1.1.2 Repetitive Pattern Generation 1 ATTERN YNCHRONIZATION 1.2.1 Synchronization...................................................................................................... 5 1.2.2 Polynomial Synchronization 1.2.3 Repetitive Pattern Synchronization 1 (BER RROR ...
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FIGURE 1-1. BLOCK DIAGRAM FIGURE 6-1. READ TIMING FIGURE 6-2. WRITE TIMING.................................................................................................................. 21 FIGURE 6-3. TRANSMIT INTERFACE FIGURE 6-4. RECEIVE INTERFACE TIMING TABLE 1-A. PIN ASSIGNMENT TABLE 2-A. REGISTER MAP TABLE 3-A. MODE SELECT................................................................................................................... 13 TABLE 3-B. ERROR BIT INSERTION.................................................................................................... ...
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GENERAL OPERATION 1.1 Pattern Generation 1.1.1 Polynomial Generation The DS2174 has a tap select register that can be used as a mask to tap bits in the feedback path of the polynomial generator. It also features ...
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Pattern Synchronization 1.2.1 Synchronization The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver ...
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Clock Discussion There are two methods for moving test patterns through a telecom network. 1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The gapped clock would be applied to ...
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Table 1-A. Pin Assignment PIN SYMBOL I VDD — 2 RCLK 3 RCLK_EN 4 RDAT0 5 RDAT1 6 RDAT2 7 RDAT3 8 RDAT4 9 RDAT5 10 RDAT6 11 RDAT7 12, 22, 29, GND — ...
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Detailed Pin Description Signal Name: RCLK Signal Description: Receive Clock Signal Type: Input Receive clock input 155MHz clock to operate the receive circuit. Input data at RDATn is sampled on the rising edge of RCLK. Signal ...
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Signal Name: TEST Signal Description: TEST Input Signal Type: Input (with internal 10kΩ pullup) Test Input. Should be left floating or held high. Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input Transmit Clock Input 155MHz ...
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PARALLEL CONTROL INTERFACE Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is ...
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CONTROL REGISTERS Control Register 1 (Address = 0h) (MSB) SYNCE RSYNC LC SYMBOL SYNC Enable SYNCE 0 = Auto resync enabled 1 = Auto resync disabled Initiate Manual Resync Process. A rising edge causes the device to go RSYNC ...
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Control Register 2 (Address = 1h) (MSB) MODE1 MODE0 TINV SYMBOL MODE1 Mode Select Bit 1 (Table 3-A) MODE0 Mode Select Bit 0 (Table 3-A) Transmit Data Inversion Select TINV not invert outbound data 1 = Invert ...
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Mode Select The DS2174 is configured to operate in bit, nibble, or byte mode by using the MODE1/MODE0 bits in Control Register 2. Table 3-A. Mode Select MODE1 MODE0 OPERATION MODE ...
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Control Register 3 (Address = 2h) (MSB) PL7 PL6 SYMBOL PL7 Pattern Length Bit 7. Bit 7 of [8:0] end address of repetitive pattern data. PL6 Pattern Length Bit 6. Bit 6 of [8:0] end address of repetitive pattern data. ...
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Status Register The status register contains information about the real-time status of the DS2174. When a particular event has occurred, the appropriate bit in the register is set All of the bits in this register (except ...
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Table 3-C. Pseudorandom Pattern Generation PATTERN TYPE 3 2 – 1 (Notes 1 and – 1 (Note – 1 (Note – 1 (Note – 1 Fractional T1 LB ...
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Test Register Test register used for factory test. All bits must be set to 0 for proper operation. Test Register (Address = 9h) (MSB) TEST TEST TEST SYMBOL TEST Factory Use. Must be set to 0 for proper operation. ...
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RAM ACCESS 4.1 Indirect Addressing 512 bytes of memory, which is addressed indirectly, are available for repetitive patterns. Data bytes are loaded one at a time into the indirect address register at address 0Fh. The RAM mode control bit, ...
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DC OPERATION ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS2174QN Storage Temperature Range Soldering Temperature Range This a stress rating only and functional operation of the device at these or any ...
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AC TIMING CHARACTERISTICS 6.1 Parallel Port Figure 6-1. Read Timing A[3:0] t SU( SU(2) RD D[7:0] DATA OUT Table 6-A. PARALLEL PORT READ TIMING (V = 3.0V to 3.6V 0°C to +70°C for DS2174Q; V ...
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Figure 6-2. Write Timing A[3:0] t SU( SU(2) WR D[7:0] DATA IN Table 6-B. PARALLEL PORT WRITE TIMING (V = 3.0V to 3.6V 0°C to +70°C for DS2174Q for DS2174QN) PARAMETER CS Setup ...
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Data Interface Figure 6-3. Transmit Interface Timing TCLK TCLK_EN t PWH(1) TCLKO DATA OUT TDAT Table 6-C. TRANSMIT DATA TIMING (V = 3.0V to 3.6V for DS2174QN) PARAMETER TCLK Clock Period (Nibble/Byte Mode) TCLK ...
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Figure 6-4. Receive Interface Timing t RCLK t H(2) t SU(2) RDAT RCLK_EN Table 6-D. RECEIVE DATA TIMING (V = 3.0V to 3.6V 0° for DS2174QN) PARAMETER RCLK Clock Period (Nibble/Byte Mode) RCLK High ...
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MECHANICAL DIMENSIONS ...