ISPGDX160A-5Q208 Lattice, ISPGDX160A-5Q208 Datasheet

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ISPGDX160A-5Q208

Manufacturer Part Number
ISPGDX160A-5Q208
Description
Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
Manufacturer
Lattice
Datasheet

Specifications of ISPGDX160A-5Q208

Mounting Style
Through Hole
Number Of Arrays
1
Operating Supply Voltage
5 V
Supply Type
Single
Configuration
160 x 160
Package / Case
DIP-24
Input Level
TTL
Output Level
TTL
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPGDX160A-5Q208
Manufacturer:
LATTICE
Quantity:
265
Part Number:
ISPGDX160A-5Q208
Manufacturer:
LATTICE
Quantity:
20 000
ispGDX
June 2010
Product Change Notification (PCN) #09-10 has been issued to discontinue select devices
in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
ispGDX160VA
Product Line
ispGDX160V
Select Devices Discontinued!
5555 N.E. Moore Ct.
®
160V/VA Device Datasheet
ispGDX160V-5B272
ispGDX160V-7B272
ispGDX160V-5B208
ispGDX160V-7B208
ispGDX160V-5Q208
ispGDX160V-7Q208
ispGDX160V-7Q208I
ispGDX160VA-3B272
ispGDX160VA-5B272
ispGDX160VA-7B272
ispGDX160VA-5B272I
ispGDX160VA-7B272I
ispGDX160VA-9B272I
ispGDX160VA-3Q208
ispGDX160VA-5Q208
ispGDX160VA-7Q208
ispGDX160VA-5Q208I
ispGDX160VA-7Q208I
ispGDX160VA-9Q208I
ispGDX160VA-3B208
ispGDX160VA-3BN208
ispGDX160VA-5B208
ispGDX160VA-5BN208
ispGDX160VA-7B208
ispGDX160VA-7BN208
ispGDX160VA-5B208I
ispGDX160VA-5BN208I
ispGDX160VA-7B208I
ispGDX160VA-7BN208I
ispGDX160VA-9B208I
ispGDX160VA-9BN208I
Ordering Part Number
Hillsboro, Oregon 97124-6421
Internet: http://www.latticesemi.com
Phone (503) 268-8000
Active / Orderable
Active / Orderable
Product Status
Discontinued
Discontinued
FAX (503) 268-8347
Reference PCN
PCN#09-10
PCN#09-10

Related parts for ISPGDX160A-5Q208

ISPGDX160A-5Q208 Summary of contents

Page 1

... N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Active / Orderable Discontinued Active / Orderable Phone (503) 268-8000 Internet: http://www.latticesemi.com Reference PCN PCN#09-10 PCN#09-10 FAX (503) 268-8347 ...

Page 2

... LEAD-FREE PACKAGE OPTIONS * “VA” Version Only Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 3

Description (Continued) found in each I/O cell. Each output has individual, pro- grammable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer con- trol (MUX0 and MUX1) inputs. Polarity for these signals is programmable for ...

Page 4

Architecture The ispGDXV/VA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program- mable interconnect consists of a single Global Routing ® Pool (GRP). Unlike ispLSI devices, there ...

Page 5

I/O MUX Operation MUX1 MUX0 Data Input Selected Flexible mapping of MUXsel to MUX x change the MUX select assignment after the ispGDXV/ VA device has been soldered to the board. Figure ...

Page 6

... D18 D17 D21 D22 The ispGDX160VA has a device ID different from the D22 D23 ispGDX160V requiring that the latest Lattice download software be used for programming and verification. Al- D23 D24 though the ispGDX160VA and ispGDX160V are D24 D25 functionally equivalent, they are not 100% JEDEC com- ...

Page 7

... Therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s CPLDs make an ideal control logic complement to the ispGDXV/VA in-system program- mable data path devices as shown below. ...

Page 8

Applications (Continued) Figure 5. Address Demultiplex/Data Buffering XCVR I/OA I/OB OEA OEB Address Latch D Q CLK Figure 6. Data Bus Byte Swapper XCVR D0-7 I/OA I/OB OEA OEB XCVR D8-15 I/OA I/OB OEA OEB Figure 7. Four-Port Memory Interface ...

Page 9

... Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions ...

Page 10

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See Figure 8) 3.3V TEST CONDITION R1 ...

Page 11

DC Electrical Characteristics for 2.5V Range SYMBOL PARAMETER V I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set ...

Page 12

External Timing Parameters TEST 1 # PARAMETER COND Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX sel A 2 Data Prop. Delay from MUXsel Inputs to Any Output ...

Page 13

External Timing Parameters TEST 1 # PARAMETER COND Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX sel A 2 Data Prop. Delay from MUXsel Inputs to Any Output ...

Page 14

External Timing Parameters (Continued) ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160VA Maximum Specifications ispGDX160VA apply to any signal path ...

Page 15

Internal Timing Parameters PARAMETER # Inputs t 32 Input Buffer Delay io GRP t 33 GRP Delay grp MUX t 34 I/O Cell MUX A/B/C/D Data Delay muxd t 35 I/O Cell MUX A/B/C/D Expander Delay muxexp t 36 I/O ...

Page 16

Internal Timing Parameters PARAMETER # Inputs t 32 Input Buffer Delay io GRP t 33 GRP Delay grp MUX t 34 I/O Cell MUX A/B/C/D Data Delay muxd t 35 I/O Cell MUX A/B/C/D Expander Delay muxexp t 36 I/O ...

Page 17

... Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions ...

Page 18

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 153Ω Active High B ...

Page 19

External Timing Parameters 1 TEST # PARAMETER COND Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX sel A Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 2 ...

Page 20

External Timing Parameters (Continued) ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160V Maximum Specifications ispGDX160V apply to any signal path ...

Page 21

Internal Timing Parameters PARAMETER # Inputs t 32 Input Buffer Delay io GRP t 33 GRP Delay grp MUX t 34 I/O Cell MUX A/B/C/D Data Delay muxd t 35 I/O Cell MUX A/B/C/D Expander Delay muxexp t 36 I/O ...

Page 22

Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...

Page 23

Development System The ispLEVER Development System supports ispGDX design using a VHDL or Verilog language syntax. From creation to in-system programming, the ispLEVER sys- tem is an easy-to-use, self-contained design tool. Features • VHDL and Verilog Synthesis Support Available ...

Page 24

Boundary Scan The ispGDXV/VA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. The boundary scan circuitry on the ispGDXV/VA Family operates independently of the programmed pattern. This Figure 10. Boundary ...

Page 25

... The ispJTAG programming is accomplished by execut- ing Lattice private instructions under the Boundary Scan State Machine. Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain Figure 11. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN ...

Page 26

Boundary Scan (Continued) Figure 13. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out Symbol t TCK [BSCAN test] clock pulse width btcp t TCK [BSCAN test] pulse ...

Page 27

Signal Descriptions Signal Name I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and ...

Page 28

Signal Locations: ispGDX160V/VA Signal 208-Pin PQFP TOE 178 RESET 185 Y0/CLKEN0 75 Y1/CLKEN1 76 Y2/CLKEN2 180 Y3/CLKEN3 181 EPEN 183 TDI 81 TCK 80 TMS 79 TDO 78 GND 6, 15, 25, 35, 44, 54, 63, 77, 91, 100, 110, ...

Page 29

I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA VCC I/O A0 CLK/CLKEN I/O A2 MUXsel1 4 C2 I/O A3 ...

Page 30

I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O A3 MUXsel2 5 A1 I/O D39 MUXsel2 208 A2 I/O D36 CLK/CLKEN 205 A3 I/O D33 OE 201 A4 I/O D30 ...

Page 31

I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O D36 CLK/CLKEN 205 A3 A3 I/O D34 MUXsel1 202 B4 A4 I/O D30 MUXsel1 198 A5 A5 I/O D24 CLK/CLKEN 190 ...

Page 32

Signal Configuration: ispGDX160V/VA ispGDX160V/VA 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O ...

Page 33

Signal Configuration: ispGDX160V/VA ispGDX160V/VA 208-Ball fpBGA Signal Diagram I/O I/O I/O I/O I D13 I/O I/O I/O I/O I D11 I/O I/O I/O I/O I/O ...

Page 34

Pin Configuration: ispGDX160V/VA ispGDX160V/VA 208-Pin PQFP Pinout Diagram Data Control — 1 VCC CLK/CLKEN I I MUXsel1 I MUXsel2 5 I — GND 6 7 CLK/CLKEN I/O A ...

Page 35

Part Number Description ispGDX XXXXX Device Family Device Number 160V 160VA Speed 3 = 3.5ns Tpd 5 = 5ns Tpd 7 = 7ns Tpd 9 = 9ns Tpd Ordering Information Conventional Packaging FAMILY tpd (ns) 3.5 3.5 3 ...

Page 36

Ordering Information (Cont.) Conventional Packaging (Cont.) FAMILY tpd (ns ispGDXVA ispGDXV* 7 *Use ispGDX160VA for new designs. Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial ...

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