LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet

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... Kbyte External Memory LAN91C100-FD for 208-pin QFP package LAN91C100-FD-SS for 208-pin QFP lead-free RoHS compliant package LAN91C100-FD for 208-pin TQFP package LAN91C100-FD-ST for 208-pin TQFP lead-free RoHS compliant package SMSC LAN91C100FD Rev. D LAN91C100FD REV. D FEAST Fast Ethernet Controller with Full Duplex Capability ...

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... OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 2 DATASHEET SMSC LAN91C100FD Rev. D ...

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... Chapter 10 Package Outlines............................................................................................................. 76 List of Figures Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13 Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14 Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18 Figure 5.1 - Data Packet Format ..................................................................................................................................19 Figure 5.2 - Interrupt Structure .....................................................................................................................................37 Figure 5.3 - Interrupt Service Routine ..........................................................................................................................44 Figure 5 INTR ...................................................................................................................................................45 Figure 5 INTR....................................................................................................................................................46 Figure 5 ...

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... Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................57 Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................59 Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................62 Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................66 Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................67 Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................68 Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................69 Figure 9.5 - Burst Read Cycles - nVLBUS=1 ...............................................................................................................70 Figure 9 ...

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... For this first generation of products, flexibility dominates over integration. The LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps ...

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... D23 GND 122 D24 121 GND 120 VDD 119 D25 118 D26 117 GND 116 D27 115 D28 114 D29 113 D30 112 GND 111 D31 110 nRDYRTN 109 nLDEV 108 VDD 107 nSRDY 106 LCLK 105 SMSC LAN91C100FD Rev. D ...

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... I with Input. When low, the LAN91C100FD pullup synchronous bus interface is configured for VL Bus accesses. Otherwise, the LAN91C100FD is configured for EISA DMA burst accesses. Does not affect the asynchronous bus interface. I Input. Used to interface synchronous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode ...

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... AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C100FD 32 bits at a time. Output. 4 μsec clock used to shift data in and O4 out of the serial EEPROM. O4 Output. Serial EEPROM chip select. Used for selection and command framing of the serial EEPROM ...

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... RAM. O4 Outputs. Active low signals used to write any byte, word or dword in RAM. O4 Output. This pin is active during LAN91C100FD write memory cycles of receive packets. Iclk An external 25 MHz crystal is connected across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open ...

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... I with Input. Transmit clock input from MII. Nibble rate pullup clock (25 MHz). This pin is ignored when MIISEL is low. I with Input. Receive clock input from MII PHY. Nibble pullup rate clock. This pin is ignored when MIISEL is low. Page 10 DATASHEET SMSC LAN91C100FD Rev. D ...

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... DMAed to memory or if asserted during the last DMA write to memory. Works for both MII and ENDEC. The typical use of nRXDISC is with the LAN91C100FD in PRMS mode with an external associative memory use for address filtering. *Note: The pin must be asserted for a minimum of 80ns. ...

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... Input buffer with TTL levels IS Input buffer with Schmitt Trigger Hysteresis Iclk Clock input buffer DC levels and conditions defined in the DC Electrical Characteristics section. Table 3.1 - LAN91C100FD Pin Requirements FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM RAM Data Bus ...

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... EEPROM Address BUS Data INTERFACE UNIT Control RD WR FIFO FIFO SMSC LAN91C100FD Rev. D ARBITER DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz Figure 3.1 - LAN91C100FD Block Diagram Page 13 DATASHEET 10 Mb Interface MEDIA 100 Media ACCESS Independent Interface CONTROL Revision 1.0 (09-22-08) ...

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... SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL DATA DATA RA Figure 3.2 - LAN91C100FD System Diagram Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability SERIAL EEPROM 1O Mbps LAN91C100FD FEAST MII OE,WE RD0-31 OR SRAM 3 4 32kx8 2 1 Page 14 DATASHEET LAN83C69 10BASE-T 10BASE-T ...

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... The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement. The external memory used is a 25ns SRAM. SMSC LAN91C100FD Rev. D Page 15 DATASHEET ...

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... For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. In 100 Mbps mode, the LAN91C100FD provides the following interface signals to the PHY: For transmission: TXEN100 TXD0-3 TX25 For reception: RX_DV RX_ER RXD0-3 RX25 ...

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... Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C100FD will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. ...

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... EEPROM EEPROM INTERFACE DATA BUS ADDRESS BUS BUS INTERFACE CONTROL WRITE DATA REG Figure 4.1 - LAN91C100FD Internal Bock Diagram with Data Path Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability RX TX FIFO DMA FIFO TX COMPL FIFO ARBITER READ ...

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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. SMSC LAN91C100FD Rev. D STATUS reserved BYTE ...

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... CPU, including the source address. The LAN91C100FD does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100FD treated transparently as data both for transmit and receive operations. ...

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... Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. SMSC LAN91C100FD Rev. D HASH VALUE 5-0 000 000 ...

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... Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C100FD. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Table 5.1 - Internal I/O Space Mapping ...

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... CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C100FD will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation. ...

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... LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in loopback mode. TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C100FD will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. BANK 0 ...

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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C100FD’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). ...

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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ ONLY NUMBER OF DEFFERED SINGLE COLLISION COUNT NAME TYPE READ ONLY REGISTER FREE MEMORY AVAILABLE (IN BYTES * 256 * MEMORY SIZE (IN BYTES *256 * Page 26 DATASHEET SYMBOL ECR SYMBOL MIR SMSC LAN91C100FD Rev. D ...

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... The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i ...

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... INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated. INT SEL1 BANK 1 OFFSET 2 BASE ADDRESS REGISTER This register holds the I/O address decode option chosen for the LAN91C100FD part of the EEPROM saved setup and is not usually modified during run-time. HIGH A15 A14 BYTE ...

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... This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C100FD. BANK 1 OFFSET C CONTROL REGISTER HIGH 0 RCV_ BAD BYTE 0 0 LOW LE CR BYTE ENABLE ENABLE 0 0 SMSC LAN91C100FD Rev. D ADDRESS ADDRESS ADDRESS ADDRESS ...

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... During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C100FD after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 μs. ...

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... N2,N1,N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2,N1,N0 are ignored by the LAN91C100FD but should be implemented in LAN91C100FD software drivers for LAN9000 compatibility. 010 ...

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... Notes: Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them ...

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... When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. SMSC LAN91C100FD Rev. D NAME TYPE ...

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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C100FD regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers ...

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... EPH INT will only be cleared by the following methods: 1. Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition. 2. Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over. SMSC LAN91C100FD Rev. D NAME WRITE ONLY REGISTER RX_OVRN INT ...

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... FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. The Receive Interrupt is cleared when RX FIFO is empty. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 36 DATASHEET SMSC LAN91C100FD Rev. D ...

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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC LAN91C100FD Rev. D Figure 5.2 - Interrupt Structure Page 37 DATASHEET Revision 1.0 (09-22-08) ...

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... FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ/WRITE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE NAME TYPE READ/WRITE MDOE Page 38 DATASHEET SYMBOL SYMBOL MGMT MCLK MDI MDO 0 MDI Pin 0 SMSC LAN91C100FD Rev. D ...

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... When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing. MBO – Must be 1. SMSC LAN91C100FD Rev. D NAME TYPE READ ONLY ...

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... BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C100FD when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE CYCLE AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 Otherwise Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability ...

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... EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC LAN91C100FD Rev. D MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...

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... Transmit pages are released by transmit completion. a) The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register. Page 42 DATASHEET SMSC LAN91C100FD Rev. D ...

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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C100FD Rev. D MAC SIDE A packet is received with matching address. Memory is requested from MMU. A packet number is assigned to it. Additional memory is requested if more pages are needed ...

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... Figure 5.3 - Interrupt Service Routine Page 44 DATASHEET Yes RX INTR? Call RXINTR Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Disable Allocation Interrupt Mask SMSC LAN91C100FD Rev. D ...

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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC LAN91C100FD Rev INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get Copy Specs from Upper ...

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... Write Address Pointer Register Read Status Word from RAM Yes TX Status No OK? Immediately Issue "Release" Command Update Variables Acknowledge TXINTR Read TX INT Again No TX INT = 0? Yes Restore Packet Number Return to ISR Figure 5 INTR Page 46 DATASHEET Update Statistics Re-Enable TXENA SMSC LAN91C100FD Rev. D ...

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... FEAST Fast Ethernet Controller with Full Duplex Capability TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) SMSC LAN91C100FD Rev. D TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = X & ...

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... Memory Partitioning Unlike other controllers, the LAN91C100FD does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation. ...

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... If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the LAN91C100FD, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...

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... In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C100FD and provided back to the CPU as their transmission completes. ...

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... TX EMPTY TWO INT OPTIONS TX INT ALLOC INT 'NOT EMPTY' PACKET NUMBER M.S. BIT ONLY Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU SMSC LAN91C100FD Rev. D PACKET NUMBER REGISTER 'EMPTY' TX DONE CPU ADDRESS PACK # OUT Page 51 DATASHEET 'NOT EMPTY' RX FIFO PACKET NUMBER ...

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... In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C100FD. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed ...

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... RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C100FD can be read or written until the EEPROM operation completes and both bits are clear. ...

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... CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. 11h BASE REG. 14h CONFIGURATION REG. 15h BASE REG. 18h CONFIGURATION REG. 19h BASE REG. 20h 21h 22h Figure 6 Serial EEPROM Map Page 54 DATASHEET 16 BITS IA0-1 IA2-3 IA4-5 SMSC LAN91C100FD Rev. D ...

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... VL Local Bus 32 Bit Systems On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions. ...

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... Byte 3 access Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. nLDEV is a totem pole output. nLDEV is active on valid decodes of A15-A4 and AEN=0. UNUSED PINS Page 56 DATASHEET SMSC LAN91C100FD Rev. D ...

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... M/nIO nRESET IRQn D0-D31 nRDYRTN nBE0-nBE3 nADS delay 1 LCLK nLRDY nLDEV SMSC LAN91C100FD Rev. D W/nR A2-A15 LCLK AEN RESET LAN91C100FD INTR0-INTR3 D0-D31 nRDYRTN nBE0-nBE3 nADS nCYCLE nSRDY O.C. simulated O.C. Figure 7.1 - LAN91C100FD on VL BUS Page 57 DATASHEET nLDEV Revision 1.0 (09-22-08) ...

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... High End ISA or Non-Burst EISA Machines On ISA machines, the LAN91C100FD is accessed bit peripheral. No support for XT (8 bit peripheral) is provided. The signal connections are listed in the following table: Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors ISA BUS LAN91C100FD SIGNAL ...

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... FEAST Fast Ethernet Controller with Full Duplex Capability ISA BUS A1-A15, AEN RESET VCC D0-D15 nIRQ nIORD nIOWR A0 nSBHE nIOCS16 SMSC LAN91C100FD Rev. D A1-A15, AEN RESET nBE2, nBE3 D0-D15 LAN91C100FD INTR0-INTR3 nRD nWR nBE0 nBE1 nLDEV O.C. Figure 7.2 - LAN91C100FD on ISA Bus Page 59 DATASHEET Revision 1.0 (09-22-08) ...

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... EISA 32 Bit SLAVEEISA 32 Bit Slave On EISA the LAN91C100FD is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1 ...

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... BCLK wide). EISA Bus Clock. Data transfer clock for DMA bursts. DMA Acknowledge. Active during Slave DMA cycles. Used by the LAN91C100FD as nDATACS direct access to data path. Indicates the direction and timing of the DMA cycles. High during LAN91C100FD writes, low during LAN91C100FD reads ...

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... LATCH + gates nWR BCLK nSTART nEX32 Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability A2-A15 RESET AEN D0-D31 INTR0-INTR3 LAN91C100FD nBE0-nBE3 nRD nWR LCLK nADS nLDEV O.C. Figure 7.3 - LAN91C100FD on EISA Bus Page 62 DATASHEET SMSC LAN91C100FD Rev. D ...

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... I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis I Input Buffer CLK Low Input Level High Input Level SMSC LAN91C100FD Rev. D SYMBOL MIN TYP MAX V 0.8 ILI 2.0 V IHI V ...

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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability SYMBOL MIN TYP MAX I -10 + -10 + -150 - +75 +150 - - - - -10 +10 OL Page 64 DATASHEET UNITS COMMENTS µ µ µ µ µ µ µ SMSC LAN91C100FD Rev. D ...

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... Low Output Level High Output Level Output Leakage Supply Current Active CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS nARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C100FD Rev. D SYMBOL MIN TYP MAX V 0 +10 - ...

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... High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability A1-15, AEN, nBE0-nBE3 valid t3 t1 D0-D31 valid PARAMETER Page 66 DATASHEET t5A MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...

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... Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold after nADS Rising SMSC LAN91C100FD Rev D0-D31 valid PARAMETER Page 67 DATASHEET t4 t5A MIN ...

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... Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t3 t1 D0-D31 valid PARAMETER Page 68 DATASHEET t5A MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...

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... Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling t17 nCYCLE High and W/nR High Overlap t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) SMSC LAN91C100FD Rev. D t12 t17 t20 t18 a b PARAMETER Page 69 DATASHEET ...

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... Data Delay from LCLK Rising (Read) Note 9.1 (holdt.) Note 9.2 (Setupt.) Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t12 t17 t19 a b t15 t14 MIN TYP (Note 9.1) Page 70 DATASHEET t13 c t17 MAX UNITS (Note 9.2) SMSC LAN91C100FD Rev. D ...

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... W/nR Setup to nCYCLE Active t17A W/nR Hold after LCLK Rising with nLRDY Active t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t21 nLRDY Delay from LCLK Rising SMSC LAN91C100FD Rev A1-A15, AEN, nBE0-nBE3 t25 MIN t9 A1-A15, AEN, nBE0-nBE3 t8 t16 ...

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... Setup to LCLK Rising t24 nRDYRTN Hold after LCLK Rising Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t9 A1-A15, AEN, nBE0-nBE3 t8 t10 t16 t11 PARAMETER Page 72 DATASHEET t23 t24 D0-D31 t21 t21 MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...

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... Write – RD0-RD31 Hold after nRWE0-nRWE3 Rising t39 Write – nRWE0-nRWE3 Pulse Width t54 Write – RA2-RA16 Valid to End of Write t38 Read – RA2-RA16 Valid to RD0-RD31 Valid t51 Read – RD0-RD31 Hold after RA2-RA16 Change SMSC LAN91C100FD Rev. D t50 t50 t54 t35 t38 t39 t39 t36 ...

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... RXC starts after CRS goes active. RXC stops after CRS goes inactive. 3. COL is an asynchronous input. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t30 Figure 9.10 - ENDEC Interface - 10 Mbps MIN TYP Page 74 DATASHEET MIN TYP MAX UNITS t31 t32 MAX UNITS SMSC LAN91C100FD Rev. D ...

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... RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C100FD Rev. D t27 t27 Figure 9.11 - MII Interface MIN Page 75 DATASHEET t28 t28 t28 ...

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... X Body Size 30.85 Y Span 28.10 Y body Size 0.20 Lead Frame Thickness 0.75 Lead Foot Length ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.30 Lead Width ~ Lead Shoulder Radius 0.25 Lead Foot Radius 0.08 Coplanarity Page 76 DATASHEET SMSC LAN91C100FD Rev. D ...

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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C100FD Rev. D MAX REMARK 1.60 Overall Package Height 0.15 Standoff 1 ...