LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet
LAN9220-ABZJ
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LAN9220-ABZJ Summary of contents
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... Reduced Power Modes — Numerous power management modes — Wake on LAN — Magic packet wakeup — Wakeup indicator event signal — Link Status Change SMSC LAN9220 LAN9220 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Single chip Ethernet controller — ...
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... LAN9220-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +70°C TEMP RANGE) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2010 SMSC or its subsidiaries. All rights reserved. ...
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... Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.10.3 Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.11 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.11.1 Hardware Reset Input (nRESET 3.11.2 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.11.3 Soft Reset (SRST 3.11.4 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SMSC LAN9220 3 DATASHEET Revision 2.7 (03-15-10) ...
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... TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3 System Control and Status Registers 5.3.1 ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 4 DATASHEET Datasheet SMSC LAN9220 ...
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... Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.5.13 PHY Special Control/Status 126 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.2 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 128 SMSC LAN9220 5 DATASHEET Revision 2.7 (03-15-10) ...
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... DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.1 56-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 6 DATASHEET Datasheet SMSC LAN9220 ...
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... Figure 3.7 Ethernet Frame with Length Field and SNAP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 3.8 Ethernet Frame with VLAN Tag and SNAP Header Figure 3.9 Ethernet Frame with multiple VLAN Tags and SNAP Header . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 3.2 LAN9220 Host Data Path Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 3.3 FIFO Access Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 3.4 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 3 ...
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... Table 5.6 MAC CSR Register Map 105 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 5.8 LAN9220 PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 6 ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 7.10 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 7.11 LAN9220 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 8.1 56 Pin QFN Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ...
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... The LAN9220 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9220 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Microcontroller The SMSC LAN9220 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9220 Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus ...
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... PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN9220. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. ...
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... Serial EEPROM Interface A serial EEPROM interface is included in the LAN9220. The serial EEPROM is optional and can be programmed with the LAN9220 MAC address. The LAN9220 can optionally load the MAC address automatically after hardware reset, or soft reset. ...
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... SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. The LAN9220 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9220 can be interfaced to either Big-Endian or Little-Endian processors and includes mixed endian support for FIFO accesses ...
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... VDDVARIO 56 **DENOTES A MULTIFUNCTION PIN NOTE: When HP Auto-MDIX is activated, the TPO+/- pins can function as TPI+/- and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 56-QFN Pin Configuration (Top View) SMSC LAN9220 SMSC LAN9220 56-QFN (TOP VIEW) VSS 15 DATASHEET ...
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... LAN9220 when reduced power state. VIS 1 Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9220 when reduced power state. VO8/ 1 Programmable Interrupt request. Programmable polarity, source and buffer types. ...
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... GPO3, TX_EN, TX_EN/TX_CLK TX_CLK EEPROM Chip EECS Select EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK SMSC LAN9220 BUFFER NUM TYPE PINS VIS/VO8 1 EEPROM Data: This bi-directional pin can be connected to a serial EEPROM DIO. This is optional. General Purpose Output 3: This pin can also ...
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... Note: Note: VO8/ 1 When programmed to do so, is asserted when the LAN9220 detects a wake event and is VOD8 requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note: ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9220 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then ...
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... EECS D9 40 EECLK/GPO4 D8 41 PME D7 42 nRESET EXPOSED PAD MUST BE CONNECTED TO VSS PULL-UP/PULL-DOWN RESISTOR VALUE (OHMS) 20 DATASHEET Datasheet PIN NUM PIN NAME 43 IRQ 44 TPO- 45 TPO+ 46 VDD33A 47 TPI- 48 TPI+ 49 VDD33A 50 EXRES 51 VDD33A 52 AMDIX_EN 53 VDD18A 54 XTAL2 55 XTAL1/CLKIN 56 VDDVARIO 10K 7.5K 4.7K SMSC LAN9220 ...
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... Electrical Specifications" Note 2.2 When operating at reduced VDDVARIO voltage levels (less than 3.0V), do not rely on internal pull-up and pull-down resistors to determine signal state. Refer to "External Pull-Up/Pull-Down Resistors" 2.1, "Pin List" SMSC LAN9220 Table 2.7 Buffer Types DESCRIPTION (Note 2.2) (Note 2 ...
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... Interface to the internal PHY. Checksum offload engine for calculation of layer 3 transmit and receive checksum. The transmit and receive data paths are separate within the LAN9220 from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. A third internal bus is used to access the MAC’ ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet The LAN9220 can store up to 250 Ethernet packets utilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms of allocation ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9220 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9220 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9220 packet filter function performs an imperfect address filtering against the hash table ...
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... Upon detection, the Wake-Up Frame Received bit (WUFR) in the WUCSR is set. When the host clears the WUEN bit the LAN9220 will resume normal receive operation. Before putting the MAC into the wake-up frame detection state, the host must provide the detection logic with a list of sample frames and their corresponding byte masks ...
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... Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. SMSC LAN9220 Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask ...
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... MAC examines receive data for a Magic Packet. The LAN9220 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9220 is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. ...
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... Figure 3.7 Ethernet Frame with Length Field and SNAP Header Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support L3 Packet Calculate Checksum Figure 3.5 Type II Ethernet Frame L3 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum 30 DATASHEET Datasheet SMSC LAN9220 ...
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... Note: Software applications must stop the receiver and flush the RX data path before changing the state of the RXCOE_EN or RXCOE_MODE bits. Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC Control simultaneously. SMSC LAN9220 {OUI[15:0], PID[15:0 Packet ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support COE_CR—Checksum Offload Engine Control Table 3.7). The TX checksum preamble instructs the TXCOE 3". In this example the host writes the packet data to the Section 3.12.2, "TX Command 32 DATASHEET Datasheet Register. Figure 3.17 Format". SMSC LAN9220 ...
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... If a read to the same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The LAN9220 will reset its read counters and restart a new cycle on the next read. SMSC LAN9220 Table 3 ...
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... Both the word swap function and the mixed endian control bits contain the ability to change the byte ordering of host data path accesses. endianess select logic is applied within the LAN9220. Logically, the endian control logic is applied after the word swap logic for write operations, and before the word swap logic for read operations. ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet and Status FIFO s FPO R TEN [29 _SW A P Figure 3.2 LAN9220 Host Data Path Diagram Data path operations for the various supported endianess and word swap configurations are illustrated in Figure 3.3. Table 3.8, "Endian Ordering Logic Operation" ...
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... Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) MSB LSB A[ A[ Figure 3.3 FIFO Access Byte Ordering 36 DATASHEET Datasheet LITTLE ENDIAN INTERNAL FIFO ORDER LSB HOST DATA BUS LITTLE ENDIAN INTERNAL FIFO ORDER LSB HOST DATA BUS SMSC LAN9220 0 0 ...
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... INT_STS Register. The GPT_INT hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only be cleared by writing a ‘1’ to the bit. SMSC LAN9220 FIFO Access via Data Direct FIFO Access via ...
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... EEPROM is not detected the responsibility of the host LAN Driver to set the IEEE addresses. The LAN9220 EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9220 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. ...
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... EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Figure 3.5 EEPROM ERASE Cycle Figure 3.6 EEPROM ERAL Cycle 40 DATASHEET Datasheet t CSL t CSL SMSC LAN9220 ...
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... Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN9220 Figure 3.7 EEPROM EWDS Cycle 1 ...
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... Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Figure 3.9 EEPROM READ Cycle Figure 3.10 EEPROM WRITE Cycle Figure 3.11 EEPROM WRAL Cycle 42 DATASHEET Datasheet t CSL CSL D0 t CSL D0 SMSC LAN9220 ...
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... Refer to Section 6.11, "EEPROM Timing," on page 138 3.10 Power Management The LAN9220 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.10, “Power Management States,” ...
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... Note 3.11 When the LAN9220 power saving state, a write of any data to the BYTE_TEST register will wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit in the PMT_CTRL register is cleared. ...
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... A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9220 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9220 can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Table 3.11 shows the effect of the various reset sources on the LAN9220's circuitry. Note: For proper operation, the LAN9220 must be reset on power-up via the hardware reset input (nRESET) or soft reset (SRST). To accomplish this, nRESET should be asserted for the minimum period of 30ms at power-up. Alternatively, a soft reset may be performed following power-up by setting the SRST bit of the HW_CFG register once the READY bit in the PMT_CTRL register has been set ...
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... PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high. After the “READY” bit is set, the LAN9220 can be configured via its control registers. The nRESET signal is pulled-high internally by the LAN9220 and can be left unconnected if unused. If used, ...
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... Buffer End Alignment field specified in each TX command. The host can instruct the LAN9220 to issue an interrupt when the buffer has been fully loaded into the TX FIFO contained in the LAN9220 and transmitted. This feature is enabled through the TX command ‘ ...
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... TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32- bit values that are used by the LAN9220 in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure ...
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... Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.14 TX Buffer Format Format", shows the TX Buffer written into the LAN9220. It should be for a detailed explanation on calculating the 51 DATASHEET 0 Section 3.12.5, Revision 2.7 (03-15-10) ...
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... This value, along with the Buffer End Alignment field, is read and checked by the LAN9220 and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9220 of the cumulative buffer sizes for a given packet. ...
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... TX Buffer Fragmentation Rules Transmit buffers must adhere to the following rules: Each buffer can start and end on any arbitrary byte alignment The first buffer of any transmit packet can be any length SMSC LAN9220 Table 3.13 TX Command 'B' Format DESCRIPTION Register, the TX checksum offload engine (TXCOE) Table 3.14, " ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9220. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... Payload from each buffer within a Packet is written into the TX data FIFO. Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the TX data FIFO SMSC LAN9220 DESCRIPTION 55 DATASHEET ...
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... End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 56 DATASHEET Datasheet SMSC LAN9220 ...
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... Buffer End Alignment = 1 Data Start Offset = 10 First Segment = 0 Last Segment = 1 Buffer Size = 17 TX Com m and 'B' Packet Length = 111 SMSC LAN9220 illustrates the TX command structure for this example, and also shows Data Written to the 0 TX Command 'A' Data Passed to the TX Command 'B' 7-Byte Data Start Offset ...
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... Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3.16 TX Example 2 58 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 183-Byte Payload Data NOTE: Extra bytes between buffers are not transmitted SMSC LAN9220 ...
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... Note: In order to perform a TX checksum calculation on the associated packet, bit 14 (CK) of the TX Command ‘B’ must be set in conjunction with bit 13 (FS Command ‘A’ and bit 16 (TXCOE_EN) of the COE_CR register. For more information, refer to Checksum Offload Engine SMSC LAN9220 illustrates the TX command structure for this example, and also shows (TXCOE)". 59 DATASHEET Section 3.6.2, " ...
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... Figure 3.17 TX Example 3 60 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' TX Checksum Preamble TX Command 'A' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes between buffers are not transmitted SMSC LAN9220 ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9220 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9220 is operating in a system that always performs multi-DWORD bursts ...
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... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support init Idle RX Interrupt Read RX Status DWORD Not Last Packet Read RX Packet init Read RX_FIFO_ INf Valid Status DWORD Read RX Status DWORD Not Last Packet Last Packet Read RX Packet 62 DATASHEET Datasheet SMSC LAN9220 ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9220 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
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... It is assumed that the host has previously read the associated 31 Optional offset DWORD0 1st 2nd . . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD Optional Pad DWORD0 . . Optional Pad DWORDn Figure 3.20 RX Packet Format (RXCOE)". 64 DATASHEET Datasheet 0 COE_CR—Checksum Offload Engine Section 3.6.1, "Receive SMSC LAN9220 ...
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... Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR Bit [16] is set. 10 Multicast Frame. When set, this bit indicates that the received frame has a Multicast address. 9:8 Reserved. These bits are reserved. Reads 0. SMSC LAN9220 31 Order Optional offset DWORD0 1st 2nd ...
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... A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support DESCRIPTION 66 DATASHEET Datasheet SMSC LAN9220 ...
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... F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is th bypassed the 5 transmit data bit is equivalent to TX_ER. SMSC LAN9220 100M PLL 4B/5B 25MHz MII ...
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... Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID 68 DATASHEET Datasheet TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN9220 ...
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... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN9220 Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 69 ...
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... Decoder 125 Mbps Serial recovery, Equalizer MLT-3 and BLW Correction Magnetics RJ45 MLT-3 MLT-3 6 bit Data Figure 4.2 Receive Data Path Figure 4.2. Detailed descriptions are given below. 70 DATASHEET Datasheet Descrambler 25MHz by 5 bits and SIPO DSP: Timing CAT-5 SMSC LAN9220 ...
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... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted SMSC LAN9220 71 DATASHEET ...
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... Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 72 DATASHEET Datasheet SMSC LAN9220 ...
Page 73
... Auto-negotiation will also re-start if not all of the required FLP bursts are received. Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new SMSC LAN9220 73 DATASHEET ...
Page 74
... Parallel Detection If the LAN9220 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
Page 75
... Mbps Note 4.1 The LAN9220 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, the internal CRS stays low and does not indicate carrier detection ...
Page 76
... The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9220 is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support ...
Page 77
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 5 Register Description The following section describes all LAN9220 registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h ...
Page 78
... LAN9220 registers accordingly. 5.2 RX and TX FIFO Ports The LAN9220 contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data ...
Page 79
... ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED SMSC LAN9220 Map", lists the registers that are directly addressable by the host Table 5.1 Direct Address Register Map CONTROL AND STATUS REGISTERS REGISTER NAME Chip ID and Revision. Main Interrupt Configuration Interrupt Status ...
Page 80
... This bit has no effect on any internal interrupt status bits. 7-5 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 50h Size: DESCRIPTION 54h Size: DESCRIPTION 80 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 9220h RO 0000h 32 bits TYPE DEFAULT R R SMSC LAN9220 ...
Page 81
... IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function as an open-drain buffer for use in a Wired-Or Interrupt configuration. When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. SMSC LAN9220 DESCRIPTION 81 DATASHEET TYPE ...
Page 82
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9220. The LAN9220 will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 83
... FIFO is full Status FIFO Level Interrupt (RSFL). Generated when the RX Status FIFO reaches the programmed level. 2-0 GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. SMSC LAN9220 DESCRIPTION 83 DATASHEET TYPE DEFAULT RO ...
Page 84
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 5Ch Size: DESCRIPTION 84 DATASHEET Datasheet 32 bits TYPE DEFAULT R R/W 0 R R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R R/W 0 R/W 0 R/W 0 R R/W 0 R/W 0 R/W 000 SMSC LAN9220 ...
Page 85
... RX Status Level. The value in this field sets the level, in number of DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be generated. When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. SMSC LAN9220 64h Size: DESCRIPTION ...
Page 86
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9220 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 87
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9220 Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’ ...
Page 88
... Section 5.3.9.1, "Allowable settings for for more information software reset is attempted when the PHY 88 DATASHEET Datasheet 32 bits Section and Section 3.13.4, "Stopping and TYPE DEFAULT R/W 0 NASR R/W 0 NASR Section AMDIX Strap Pin RO R SMSC LAN9220 ...
Page 89
... After a PHY reset, or when returning from a reduced power state, the PHY must given adequate time to return to the operational state before a soft reset can be issued. The LAN9220 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. SMSC LAN9220 ...
Page 90
... DATASHEET Datasheet RX STATUS FIFO SIZE (BYTES) SIZE (BYTES) 13440 896 12480 832 11520 768 10560 704 9600 640 8640 576 7680 512 6720 448 5760 384 4800 320 3840 256 2880 192 1920 128 SMSC LAN9220 ...
Page 91
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9220 moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 92
... RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9220 Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. 15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO ...
Page 93
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9220 Note: The LAN9220 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS 31:14 ...
Page 94
... Device Ready (READY). When set, this bit indicates that LAN9220 is ready to be accessed. This register can be read when LAN9220 is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9220 has stabilized and is fully alive ...
Page 95
... GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as output. When cleared the GPIO is enabled as an input. GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 7:5 Reserved SMSC LAN9220 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 95 DATASHEET ...
Page 96
... Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 TX_EN TX_EN TX_CLK 8Ch Size: DESCRIPTION 96 DATASHEET Datasheet TYPE DEFAULT R/W 00 R/W 000 EECLK FUNCTION EECLK GPO4 Reserved RX_DV Reserved GPO4 RX_DV RX_CLK 32 bits TYPE DEFAULT R/W FFFFh SMSC LAN9220 ...
Page 97
... This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN9220. The LAN9220 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 98
... An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION 98 DATASHEET Datasheet 32 bits TYPE DEFAULT bits TYPE DEFAULT RC 00000000h SMSC LAN9220 ...
Page 99
... MAC_CSR_DATA – MAC CSR Synchronizer Data Register Offset: This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s BITS 31-0 MAC CSR Data. Value read from or written to the MAC CSR’s. SMSC LAN9220 A4h Size: DESCRIPTION A8h Size: DESCRIPTION ...
Page 100
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9220 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 ...
Page 101
... Datasheet BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9220 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9220 is operating in full-duplex mode. ...
Page 102
... MAC address from the EEPROM the EPC Busy bit is cleared. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support B0h Size: DESCRIPTION 102 DATASHEET Datasheet 32 bits TYPE DEFAULT SC 0 SMSC LAN9220 ...
Page 103
... MAC address from the EEPROM value of 0xA5 is not found in the first address of the EEPROM, the EEPROM is assumed to be un- programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. SMSC LAN9220 DESCRIPTION [28] OPERATION 0 0 ...
Page 104
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 104 DATASHEET Datasheet TYPE DEFAULT R/WC 0 R/WC - R/W 00h 32 bits TYPE DEFAULT RO - R/W 00h SMSC LAN9220 ...
Page 105
... VLAN1 A VLAN2 B WUFF C WUCSR D COE_CR SMSC LAN9220 Map", shown below, lists the MAC registers that are Table 5.6 MAC CSR Register Map REGISTER NAME MAC Control Register MAC Address High MAC Address Low Multicast Hash Table High Multicast Hash Table Low ...
Page 106
... Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 1 Attribute: 00040000h Size: DESCRIPTION 106 DATASHEET Datasheet R/W 32 bits SMSC LAN9220 ...
Page 107
... Datasheet BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9220 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 108
... When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. 1-0 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support DESCRIPTION BOLMT Value # Bits Used from LFSR Counter 2’b00 2’b01 2’b10 2’b11 108 DATASHEET Datasheet SMSC LAN9220 ...
Page 109
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9220 device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. ...
Page 110
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9220 device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 111
... HASHL—Multicast Hash Table Low Register Offset: Default Value: This register defines the lower 32-bits of the Multicast Hash Table. Please refer to "HASHH—Multicast Hash Table High Register" BITS 31-0 Lower 32 bits of the 64-bit Hash Table SMSC LAN9220 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: ...
Page 112
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9220 to read or write any of the MII PHY registers. ...
Page 113
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9220 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 114
... Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 9 Attribute: 00000000h Size: DESCRIPTION A Attribute: 00000000h Size: DESCRIPTION 114 DATASHEET Datasheet R/W 32 bits R/W 32 bits SMSC LAN9220 ...
Page 115
... Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is capable of detecting wake-up frames as programmed in the wake-up frame filter. 1 Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved SMSC LAN9220 B Attribute: 00000000h Size: DESCRIPTION C Attribute: ...
Page 116
... MAC_CR—MAC Control simultaneously. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support D Attribute: 00000000h Size: DESCRIPTION Register) and vice versa. These functions cannot be enabled 116 DATASHEET Datasheet R/W 32 bits SMSC LAN9220 ...
Page 117
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9220 PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 118
... The default value of this bit is determined by the auto-negotiation process. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 0 Size: DESCRIPTION 118 DATASHEET Datasheet 16-bits TYPE DEFAULT RW/ See Note 5 RW/ See Note 5 SMSC LAN9220 ...
Page 119
... Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. 5.5.3 PHY Identifier 1 Index (In Decimal): BITS 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN9220 1 Size: DESCRIPTION 2 Size: DESCRIPTION 119 DATASHEET ...
Page 120
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5.2) 120 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0xC0C3h RO RO 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W 1 R/W 1 R/W 1 R/W 1 R/W 00001 SMSC LAN9220 ...
Page 121
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9220 5 Size: DESCRIPTION 121 DATASHEET 16-bits TYPE DEFAULT ...
Page 122
... The default value of this bit will vary dependant on the current link state of the line. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 6 Size: DESCRIPTION 17 Size: DESCRIPTION 122 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT See Note 5 SMSC LAN9220 ...
Page 123
... Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9220 in this mode. 111 All capable. Auto-negotiation enabled. Note 5.4 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto- negotiated speed and duplex. ...
Page 124
... Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 27 Size: DESCRIPTION 124 DATASHEET Datasheet 16-bits MODE DEFAULT RW, 0 NASR XXXXb SMSC LAN9220 ...
Page 125
... The default value of this bit will vary dependant on the current link state of the line. 5.5.12 Interrupt Mask Index (In Decimal): BITS 15-8 Reserved. Write as 0; ignore on read. 7-0 Mask Bits interrupt source is enabled 0 = interrupt source is masked SMSC LAN9220 29 Size: DESCRIPTION 30 Size: DESCRIPTION 125 DATASHEET ...
Page 126
... The default value of this bit is determined by the auto-negotiation process. Revision 2.7 (03-15-10) 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support 31 Size: DESCRIPTION 126 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 000b 0000010b RO See Note 5.6 RO 00b SMSC LAN9220 ...
Page 127
... Output timing specifications assume an equivalent test load as illustrated in OUTPUT 6.2 Host Interface Timing The LAN9220 supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Reads (nCS or nRD controlled) ...
Page 128
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9220 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 129
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9220, and the subsequent indication of the expected change in the control register values. ...
Page 130
... Figure 6.2 PIO Read Cycle Timing Table 6.3 PIO Read Timing time is 9ns. doff and t must be extended using wait states to meet the t csl 130 DATASHEET Datasheet MIN TYP MAX UNITS 165 133 Note 6 time is 7ns. When VDDVARIO is doff minimum. cycle SMSC LAN9220 ...
Page 131
... Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9220 Figure 6.3 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing time is 9ns ...
Page 132
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9220 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9220 ...
Page 133
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9220 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9220 ...
Page 134
... PIO Writes PIO writes are used for all LAN9220 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] nCS, nWR Data Bus Note: The “ ...
Page 135
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9220 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9220 ...
Page 136
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support t pon Figure 6.8 Power Sequence Timing Table 6.9 Power Sequence Timing MIN TYP 136 DATASHEET Datasheet . Device pon t poff MAX UNITS NOTES 50 ms 500 ms SMSC LAN9220 ...
Page 137
... T6.1 Reset Pulse Width T6.2 Configuration input setup to nRESET rising T6.3 Configuration input hold after nRESET rising T6.4 Output Drive after nRESET rising SMSC LAN9220 T6.1 T6.2 T6.3 T6.4 Figure 6.9 Reset Timing Table 6.10 Reset Timing MIN TYP MAX 30 200 ...
Page 138
... EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9220: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK CSHCKH t EECLK falling edge to EECS low CKLCSL t EEDIO valid before rising edge of EECLK ...
Page 139
... Supply Voltage (VDDVARIO +1.62V to +3.6V Supply Voltage (VDD33REG, VDD33A +3.3V+/-300mV Ambient Operating Temperature in Still Air (T Note: Do not drive input signals without power supplied to the device. **Proper operation of the LAN9220 is guaranteed only within the ranges specified in this section. SMSC LAN9220 (Note 7. +3.6V (Note 7 ...
Page 140
... Power Consumption (Device Only) This section provides typical power consumption values for the LAN9220 in various modes of operation. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD (VDDVARIO, VDD33REG, VDD33A): ....................................................................... +3.30V Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements ...
Page 141
... Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9220, including the power dissipated by the magnetics and other passive components. Note: The power measurements list below were taken under the following conditions: Temperature: ................................................................................................................................... +25° ...
Page 142
... VDD33REG 3.6V VDD33A 3.6V SUPPLY NAME SUPPLY VOLTAGE VDDVARIO 2.75V VDD33REG 3.6V VDD33A 3.6V SUPPLY NAME SUPPLY VOLTAGE VDDVARIO 1.98V VDD33REG 3.6V VDD33A 3.6V 142 DATASHEET Datasheet +70 C Note 7.5 MAX CURRENT UNITS MAX CURRENT UNITS MAX CURRENT UNITS SMSC LAN9220 ...
Page 143
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.6 DC Electrical Specifications This section details the DC electrical specifications of the LAN9220 I/O buffers. The electrical specifications in this section are valid over the indicated voltage range and the temperature range specified in Section 7.2, "Operating Note: When operating at reduced VDDVARIO voltage levels (less than 3 ...
Page 144
... VDDVARIO - 0.4 VDDVARIO - 0.4 -0.3 1.4 144 DATASHEET Datasheet UNITS NOTES V 5.5 V 1.1 V Schmitt Trigger V Schmitt Trigger 472 mV +10 uA Note 7.6 120 uA Note 7.6, Note 7.7 2 9mA -9mA OH 0 9mA OL 0 6mA OL 0 6mA -6mA OH 0.5 V 3.6 V SMSC LAN9220 ...
Page 145
... Description and Configuration Note 7.7 This is the total V the number of pins driven to V are driven to the maximum operational limit for V VDDVARIO), the per-pin input leakage is the maximum input leakage current divided by 10. SMSC LAN9220 MIN TYP MAX -0.3 5.25 0.54 0.69 ...
Page 146
... RFS 1.4 SYMBOL MIN TYP MAX V 2.2 2.5 2.8 OUT V 300 420 585 DS 146 DATASHEET Datasheet UNITS NOTES mVpk Note 7.8 mVpk Note 7.8 % Note 7.8 nS Note 7.8 nS Note 7.8 % Note 7 Note 7.10 UNITS NOTES V Note 7.11 mV SMSC LAN9220 ...
Page 147
... Clock Circuit The LAN9220 can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9220 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 148
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support MAX 1.00 Overall Package Height 0.05 0.90 Mold Cap Thickness 8.15 7.95 X/Y Mold Cap Size 6.05 X/Y Exposed Pad Size 0.50 0.30 148 DATASHEET Datasheet REMARKS Standoff X/Y Body Size Terminal Length Terminal Width Terminal Pitch SMSC LAN9220 ...
Page 149
... Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Figure 8.2 56 Pin QFN Recommended PCB Land Pattern SMSC LAN9220 149 DATASHEET Revision 2.7 (03-15-10) ...
Page 150
... Diagram redone. The word “Core” was added to the regulator block title. Changed VDD_CORE/VDD18CORE bulk capacitor value from 10uF to 4.7uF. Bits 9 and 15 relabeled as Reserved, Read-Only (RO), with a default of 0. 150 DATASHEET Datasheet CORRECTION SMSC LAN9220 ...
Page 151
... EECLK pin description in Chapter 2 Pin Description and Configurationon page 15 SMSC LAN9220 Fixed definition of bits 11:10 when equal to “11” by adding “advertise support for..” to beginning of definition. Also added note stating “When both symmetric PAUSE and asymmetric PAUSE support are advertised, the device will only be configured to, at most, one of the two settings upon auto-negotiation completion.” ...