DS2155G/T&R Maxim Integrated Products, DS2155G/T&R Datasheet - Page 216
DS2155G/T&R
Manufacturer Part Number
DS2155G/T&R
Description
Network Controller & Processor ICs T1/E1/J1 Single-Chip gle-Chip Transceiver
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2155L.pdf
(238 pages)
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Figure 35-16. Receive IBO Frame Interleave Mode Timing
Note 1: 4.096MHz bus configuration.
Note 2: 8.192MHz bus configuration.
Note 3: 16.384MHz bus configuration.
Note 4: RSYNC is in the input mode (IOCR1.4 = 0).
RSYSCLK
RSYNC
RSYNC
RSER
RSIG
RSER
RSER
RSER
RSIG
RSIG
RSIG
4
1
1
2
2
3
3
FRAMER2, CHANNEL 32
FRAMER2, CHANNEL 32
F5
F5
F3
F3
F6
F6
A
F2
F2
F7
F7
F4
B
F4
F8
F8
C
BIT LEVEL DETAIL (4.096MHz bus configurtation)
F1
F1
LSB
D
F1
F1
F2
F2
MSB
F1
F1
F3
F3
FRAMER #1, CHANNELS 1 through 32
FRAMER 1, CHANNEL 1
F2
F2
FRAMER 1, CHANNEL 1
F4
F4
216 of 238
F5
F5
F3
F3
F6
A
F6
F2
F2
F7
B
F7
F4
F4
C
F8
F8
LSB
D
F1
F1
F1
F1
MSB
F2
F2
F1
F1
F3
FRAMER1, CHANNEL 2
FRAMER1, CHANNEL 2
F3
F2
F2
F4
F4
F5
F5
F3
F3
A
F6
F6
F2
F2
B
F7
F7
C
F4
F4
F8
F8
LSB
D
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