LAN8700I-AEZG SMSC, LAN8700I-AEZG Datasheet
LAN8700I-AEZG
Specifications of LAN8700I-AEZG
Related parts for LAN8700I-AEZG
LAN8700I-AEZG Summary of contents
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... Low profile 36-pin QFN lead-free RoHS compliant package ( 0.9mm height) 4 LED status indicators Commercial Operating Temperature 0° 70° C Industrial Operating Temperature -40° 85° C version available (LAN8700i) SMSC LAN8700/LAN8700i LAN8700/LAN8700i ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR ...
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... LAN8700C-AEZG for 36-pin, QFN lead-free RoHS compliant package LAN8700iC-AEZG for (Industrial Temp) 36-pin, QFN lead-free RoHS compliant package LAN8700C-AEZG-TR for 36-pin, QFN lead-free RoHS compliant package (tape and reel) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
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... Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.3 Disabling Auto-negotiation 4.7.4 Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9 Internal +1.8V Regulator Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9.1 Disable the Internal +1.8V Regulator 4.9.2 Enable the Internal +1.8V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 nINT/TX_ER/TXD4 Strapping SMSC LAN8700/LAN8700i ® Technology in a Small Footprint 3 DATASHEET Revision 2.2 (12-04-09) ...
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... Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.4 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.5 Evaluation board Chapter 9 Package Outline, Tape and Reel Chapter 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR 4 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet List of Figures Figure 1.1 LAN8700/LAN8700i System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 1.2 LAN8700/LAN8700i Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.1 Package Pinout (Top View Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4 ...
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... List of Tables Table 2.1 LAN8700/LAN8700i 36-PIN QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.3 Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.4 Boot Strap Configuration Inputs Table 3.5 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.6 10/100 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.7 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.8 Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4 ...
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... Table 6.8 10M RMII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 6.9 10M RMII Transmit Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 6.10 RMII CLKIN (REF_CLK)Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 6.11 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.12 LAN8700/LAN8700i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 7.1 Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.2 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7 ...
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... RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock. The MII requires 16 pins for each MAC to PHY interface. The SMSC LAN8700/LAN8700i is capable of running in RMII mode. Please contact your SMSC sales representative for the latest RMII specification. ...
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... Rx TX_ER Logic TX_CLK RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M Rx CRS Logic COL/CRS_DV MDC MDIO Figure 1.2 LAN8700/LAN8700i Architectural Overview SMSC LAN8700/LAN8700i ® Technology in a Small Footprint 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR LAN8700/LAN8700I 4 MII/RMII Ethernet PHY 5 36 Pin QFN 6 GND FLAG Figure 2.1 Package Pinout (Top View) 10 DATASHEET ® Technology in a Small Footprint Datasheet 27 TXD3 26 TXD2 25 VDDIO 24 TXD1 23 TXD0 22 TX_CLK 21 RX_ER/RXD4 20 RX_CLK/REGOFF 19 RX_DV SMSC LAN8700/LAN8700i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 2.1 LAN8700/LAN8700i 36-PIN QFN Pinout PIN NO. PIN NAME 1 nINT/TX_ER/TXD4 2 MDC 3 CRS/PHYAD4 4 MDIO 5 nRST 6 TX_EN 7 VDD33 8 VDD_CORE 9 SPEED100/PHYAD0 10 LINK/PHYAD1 11 ACTIVITY/PHYAD2 12 FDUPLEX/PHYAD3 13 XTAL2 14 CLKIN/XTAL1 15 RXD3/nINTSEL 16 RXD2/MODE2 17 RXD1/MODE1 18 RXD0/MODE0 SMSC LAN8700/LAN8700i ® ...
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... See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 31 for additional information on configuration/strapping options. IPD Transmit Enable: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0] have valid data. 12 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... Datasheet SIGNAL NAME TX_CLK RXD0/ MODE0 RXD1/ MODE1 RXD2/ MODE2 RXD3/ nINTSEL SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 3.1 MII Signals (continued) TYPE DESCRIPTION O Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. Note: This signal is not used in RMII Mode. ...
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... IOPU LED1 – SPEED100 indication. Active indicates that the selected speed is 100Mbps. Inactive indicates that the selected speed is 10Mbps. Note: This signal is mux’d with PHYAD0 14 DATASHEET ® Technology in a Small Footprint Datasheet Section 4.9, this pin is sampled for SMSC LAN8700/LAN8700i ...
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... PHYAD1 SPEED100/ PHYAD0 RXD2/ MODE2 RXD1/ MODE1 RXD0/ MODE0 SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 3.2 LED Signals (continued) IOPU LED2 – LINK ON indication. Active indicates that the Link (100Base-TX or 10Base-T) is on. Note: This signal is mux’d with PHYAD1 IOPU LED3 – ...
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... Strapping options. O Clock Output – 25 MHz crystal output. Note: Float this pin if using an external clock being driven through CLKIN/XTAL1 16 DATASHEET ® Technology in a Small Footprint Datasheet Table 4.3, 32) . Table 4.3, “Boot Strapping 32) pin 1 is TX_ER/TXD4, Section 5.4.9.2. SMSC LAN8700/LAN8700i ...
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... RXP RXN SIGNAL NAME EXRES1 SIGNAL NAME VDDIO VDD33 VDDA3.3 VDD_CORE VSS SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 3.6 10/100 Line Interface TYPE DESCRIPTION AO Transmit Data Positive: 100Base-TX or 10Base-T differential transmit outputs to magnetics. AO Transmit Data Negative: 100Base-TX or 10Base-T differential transmit outputs to magnetics ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR its ria rive Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 18 DATASHEET ® Technology in a Small Footprint Datasheet S cra its tic s Table 4.1. Each 4-bit data-nibble SMSC LAN8700/LAN8700i ...
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... Second nibble of ESD, causes deassertion of CRS if following /T/, else assertion of RX_ER 00100 H Transmit Error Symbol 00110 V INVALID, RX_ER if during RX_DV 11001 V INVALID, RX_ER if during RX_DV SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 ...
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... Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 20 DATASHEET ® Technology in a Small Footprint Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN8700/LAN8700i ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint 100M PLL ...
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... Figure 4.3 Relationship Between Received Data and Specific MII Signals Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR data data data data data data data data 22 DATASHEET ® Technology in a Small Footprint Datasheet T R Idle SMSC LAN8700/LAN8700i ...
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... Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8700/LAN8700i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR 24 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... RMII The SMSC LAN8700/LAN8700i supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase ...
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... MII vs. RMII Configuration The LAN8700/LAN8700i must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the COL/RMII/CRS_DV pin. To select MII mode, float the COL/RMII/CRS_DV pin. To select RMII mode, pull the pin high with an external resistor (see “ ...
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... Speed Indication bits in register 31, as well as the Link Partner Ability Register (Register 5). The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 4.2, "MII/RMII Signal Table 4.2 MII/RMII Signal Mapping ...
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... Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR 28 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... Parallel Detection If the LAN8700/LAN8700i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR 32) is connected from RXCLK/REGOFF to VDDIO. At power-on, 30 DATASHEET ® Technology in a Small Footprint Datasheet Table 4.3, “Boot Strapping , IH Section 4.9.1. By default, the Table 7.11, , then the internal IL SMSC LAN8700/LAN8700i ...
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... Variable Voltage I/O The Digital I/O pins on the LAN8700/LAN8700i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10 +3.3V+10%. Due to this low voltage feature addition, the system designer needs to take consideration as for two aspects of their design ...
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... Interrupt 4.13.1 Serial Management Interface (SMI) The Serial Management Interface is used to control the LAN8700/LAN8700i and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “ ...
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... Figure 4.6 MDIO Timing and Frame Structure - READ Cycle MDC MDIO 32 1 Start of OP Preamble Frame Code Figure 4.7 MDIO Timing and Frame Structure - WRITE Cycle SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address Data To Phy 33 DATASHEET ...
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Chapter 5 Registers Reset Loopback Speed A/N Select Enable 100Base 100Base 100Base 10Base- T -T4 -TX -TX Full Half Full Duplex Duplex Duplex PHY ID Number (Bits ...
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Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended Next Reserved Remote Reserved Page Fault Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault ...
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Table 5.9 Register 8 (Extended ...
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Reserved Table 5.18 Mode Control/ Status Register 17: Vendor-Specific RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved ...
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Table 5.23 Symbol Error Counter Register 26: Vendor-Specific Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL ...
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Reserved Reserved Table 5.28 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved Table 5.26 Interrupt Source Flags Register 29: Vendor-Specific 10 ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Table 5.29 SMI Register Mapping DESCRIPTION 40 DATASHEET ® Technology in a Small Footprint Datasheet Group Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8700/LAN8700i ...
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... Duplex 1.10:6 Reserved 1.5 Auto-Negotiate 1 = auto-negotiate process completed 0 = auto-negotiate process not completed Complete SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 5.30 Register 0 - Basic Control DESCRIPTION when setting this bit do not set other bits in this register. The configuration (as described in Section 5.4.9.2) is set from the register bit values, and not from the mode pins ...
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... No PAUSE 01 = Symmetric PAUSE 10 = Asymmetric PAUSE toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local device 42 DATASHEET ® Technology in a Small Footprint Datasheet MODE DEFAULT MODE DEFAULT RW 0007h MODE DEFAULT RW C0h RW 0Ch RW 4h MODE DEFAULT R/W 00 SMSC LAN8700/LAN8700i ...
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... Full Duplex 5.7 100Base-TX 5.6 10Base-T Full Duplex 5.5 10Base-T 5.4:0 Selector Field SMSC LAN8700/LAN8700i ® Technology in a Small Footprint DESCRIPTION able ability This Phy does not support 100Base-T4 with full duplex full duplex ability able ability 1 = 10Mbps with full duplex ...
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... This bit is only active in RMII mode. In this mode the user needs to supply a 50MHz clock to the PHY. This mode works even if MII Isolate (0.10) is set. 44 DATASHEET ® Technology in a Small Footprint Datasheet MODE DEFAULT MODE DEFAULT 0001 RO 0 MODE DEFAULT SMSC LAN8700/LAN8700i ...
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... MODE 18.4:0 PHYAD Table 5.40 Register 26 - Symbol Error Counter ADDRESS NAME 26.15:0 Sym_Err_Cnt SMSC LAN8700/LAN8700i ® Technology in a Small Footprint DESCRIPTION Write as 0, ignore on read. Alternate Interrupt Mode Primary interrupt system enabled (Default Alternate interrupt system enabled. See Section 5.3, "Interrupt Management," on page Write as 0, ignore on read ...
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... Link Down (link status negated not source of interrupt 1 = Auto-Negotiation LP Acknowledge 0 = not source of interrupt 1 = Parallel Detection Fault 0 = not source of interrupt 46 DATASHEET ® Technology in a Small Footprint Datasheet MODE DEFAULT RW, 0 NASR RW 000000 XXXXb MODE DEFAULT RW N/A MODE DEFAULT SMSC LAN8700/LAN8700i ...
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... Enable 4B5B 31.5 Reserved 31.4:2 Speed Indication 31.1 Reserved 31.0 Scramble Disable SMSC LAN8700/LAN8700i ® Technology in a Small Footprint DESCRIPTION 1 = Auto-Negotiation Page Received 0 = not source of interrupt Ignore on read. Table 5.44 Register 30 - Interrupt Mask DESCRIPTION Write as 0; ignore on read interrupt source is enabled 0 = interrupt source is masked Write as 0 ...
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... Falling 1.2 Reading register 1 or Reading register 29 Rising 5.14 Falling 5.14 or Read register 29 Rising 6.4 Falling 6.4 or Reading register 6, or Reading register 29 or Re-Auto Negotiate or Link down Rising 6.1 Falling of 6.1 or Reading register 6, or Reading register 29 Re-Auto Negotiate, or Link Down. SMSC LAN8700/LAN8700i ...
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... If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by some non-IDLE symbol. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Interrupt Source ...
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... Link Integrity Test The LAN8700/LAN8700i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. ...
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... LED Description The PHY provides four LED signals. These provide a convenient means to determine the mode of operation of the Phy. All LED signals are either active high or active low. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint The first and possibly the second packet Figure 6 ...
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... The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8700/LAN8700i senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active- low. If the address bit is set as level “ ...
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... Figure 5.3 Far Loopback Block Diagram 5.4.8.3 Connector Loopback The LAN8700/LAN8700i maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Table 5.48 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES REGISTER 0 [13,12,10,8] 54 DATASHEET ® Technology in a Small Footprint Datasheet REGISTER 4 [8,7,6,5] 0000 N/A 0001 N/A 1000 N/A 1001 N/A 1100 0100 1100 0100 N/A N/A X10X 1111 SMSC LAN8700/LAN8700i ...
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... PARAMETER DESCRIPTION T1.1 MDC minimum cycle time T1.2 MDC to MDIO (Read from PHY) delay T1.3 MDIO (Write to PHY) to MDC setup T1.4 MDIO (Write to PHY) to MDC hold SMSC LAN8700/LAN8700i ® Technology in a Small Footprint T 1.1 T 1.2 Valid Data (Read from PHY) T 1.3 1 ...
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... RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR T 2.1 2.2 Valid Data MIN TYP DATASHEET ® Technology in a Small Footprint Datasheet MAX UNITS NOTES ns ns MHz % SMSC LAN8700/LAN8700i ...
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... Figure 6.3 100M MII Transmit Timing Diagram Table 6.3 100M MII Transmit Timing Values PARAMETER DESCRIPTION T3.1 Transmit signals required setup to TX_CLK rising Transmit signals required hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle SMSC LAN8700/LAN8700i ® Technology in a Small Footprint T 3.1 Valid Data MIN TYP MAX 12 0 ...
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... RX_CLK frequency RX_CLK Duty-Cycle Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR T T 4.1 4.2 Valid Data MIN TYP DATASHEET ® Technology in a Small Footprint Datasheet MAX UNITS NOTES ns ns MHz % SMSC LAN8700/LAN8700i ...
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... RMII 10/100Base-TX/RX Timings 6.3.1 RMII 100Base-T TX/RX Timings 6.3.1.1 100M RMII Receive Timing Clock In - CLKIN Data Out - RXD[1:0] CRS_DV Figure 6.6 100M RMII Receive Timing Diagram SMSC LAN8700/LAN8700i ® Technology in a Small Footprint T 5.1 Valid Data MIN TYP MAX 12 0 2.5 ...
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... Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR MIN TYP MAX 8.1 8.2 Valid Data MIN TYP MAX 2 1 DATASHEET ® Technology in a Small Footprint Datasheet UNITS NOTES ns MHz UNITS NOTES ns ns MHz SMSC LAN8700/LAN8700i ...
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... Figure 6.8 10M RMII Receive Timing Diagram Table 6.8 10M RMII Receive Timing Values PARAMETER DESCRIPTION T9.1 Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency SMSC LAN8700/LAN8700i ® Technology in a Small Footprint T 9.1 Valid Data MIN TYP MAX ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR T T 10.1 10.2 Valid Data MIN TYP MAX MIN TYP MAX 50 ± 150 62 DATASHEET ® Technology in a Small Footprint Datasheet UNITS NOTES ns ns MHz UNITS NOTES MHz ppm % psec p-p – not RMS SMSC LAN8700/LAN8700i ...
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... PARAMETER DESCRIPTION T11.1 Reset Pulse Width T11.2 Configuration input setup to nRST rising T11.3 Configuration input hold after nRST rising T11.4 Output Drive after nRST rising SMSC LAN8700/LAN8700i ® Technology in a Small Footprint T 11 11.2 11.3 T 11.4 Figure 6.10 Reset Timing Diagram Table 6 ...
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... Clock Circuit LAN8700/LAN8700i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input for operation in MII mode. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. The user is required to supply a 50MHz single-ended clock for RMII operation. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum ...
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... CONDITIONS VDD33,VDDIO Power pins to all other pins. Digital IO To VSS ground VSS VSS to all other pins Operating LAN8700-AEZG Temperature Operating LAN8700i-AEZG Temperature Storage Temperature Table 7.2 ESD and LATCH-UP Performance PARAMETER CONDITIONS All Pins Human Body Model System EN/IEC61000-4-2 Contact Discharge ...
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... Input Voltage on Digital Pins Voltage on Analog I/O pins (RXP, RXN) Ambient Temperature T LAN8700-AEZG A T LAN8700i-AEZG A 7.1.3 Power Consumption 7.1.3.1 Power Consumption Device Only Power measurements taken over the operating conditions specified. See of the power down modes. Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR ...
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... This is calculated with full flexPWR features activated: VDDIO = 1.8V and internal regulator disabled. Note 7.2 Current measurements do not include power applied to the magnetics or the optional external LEDs. Current measurements taken with VDDIO = +3.3V, unless otherwise indicated. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint VDDA3.3 VDD_CORE POWER ...
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... VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 VDDIO – +0.4 +0.4 3.6 SMSC LAN8700/LAN8700i ...
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... VDDIO FDUPLEX/PHYAD3 0.68 * VDDIO CRS/PHYAD4 0.68 * VDDIO RXD0/MODE0 0.68 * VDDIO RXD1/MODE1 0.68 * VDDIO RXD2/MODE2 0.68 * VDDIO RX_CLK/REGOFF 0.68 * VDDIO COL/RMII/CRS_DV SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 7.6 LAN Interface Signals “10BASE-T Transceiver Characteristics,” on page Table 7.7 LED Signals (V) V ...
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... VDDIO 0.4 * VDDIO - - Table 7.10 Analog References PULL-UP OR PULL-DOWN Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down 70 DATASHEET ® Technology in a Small Footprint Datasheet I V ( +0.4 VDDIO – +0 Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up SMSC LAN8700/LAN8700i ...
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... Note 7.6 Measured differentially. Table 7.13 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.7 Min/max voltages guaranteed as measured with 100Ω resistive load. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint SYMBOL MIN TYP MAX V ...
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... GND FLAG FullDuplex Activity R2 R3 Link R4 Section 8.4, "Reference 72 DATASHEET ® Technology in a Small Footprint Datasheet MII/RMII MAC Integrated Magnetics and RJ45 Jack TXD3 TXD2 26 VDDIO 25 24 TXD1 23 TXD0 22 TX_CLK RX_ER/RXD4 21 RX_CLK/REGOFF 20 RX_DV 19 VDDIO Variable Voltage IO Regulator Designs") SMSC LAN8700/LAN8700i ...
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... Full Duplex RJ-45 Connector LEDs for Link and Activity Interfaces Through 40-pin Connector as Defined in the MII Specification Powered by 5.0V from the 40-Pin MII Connector Standard RJ45 Connector with LED indicators for Link and Activity SMSC LAN8700/LAN8700i ® Technology in a Small Footprint 73 DATASHEET ...
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... Support testing of FPGA implementations of MAC Assist interoperability test of various networks Verify MII compliance Verify performance of HP AutoMDIX feature Verify Variable IO compliance Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR 74 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... Tolerance on the true position of the terminal is ± 0. maximum material conditions (MMC). 3. Details of terminal #1 identifier are optional but must be located within the zone indicated. 4. Coplanarity zone applies to exposed pad and terminals. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint MAX REMARKS 1 ...
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... Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Figure 9.2 QFN, 6x6 Tape & Reel 76 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Note: Standard reel size is 3000 pieces per reel. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Figure 9.3 Reel Dimensions 77 DATASHEET Revision 2.2 (12-04-09) ...
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... Removed the text “T3.2” in the “Parameter” column Replaced figure Changed the MIN value for T11.3: From: “400” To: “10” Deleted last row in table First sentence of second paragraph changed: From: “between 35% and 65%” To: “between 40% and 60%” 78 DATASHEET ® Technology in a Small Footprint Datasheet CORRECTION SMSC LAN8700/LAN8700i ...
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... Table 6.7 (05-23-07) Rev. 1.1 Table 7.4 (04-17-07) Rev. 1.1 Table 3.4 (04-17-07) SMSC LAN8700/LAN8700i ® Technology in a Small Footprint CORRECTION Changed value of T8.1 and T8.2 Changed value of T6.1 Added information about not applying VDD_CORE before VDD33 is at 2.64V. Updated description of VDD_CORE for information on using external 1 ...
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... R5 added. Corrected reg3 values Changed paragraph to correctly reflect operation VDDIO and VDDA latch 1.8V regulator. 1.8v strap above VIH or below VIL. 80 DATASHEET ® Technology in a Small Footprint Datasheet CORRECTION SMSC LAN8700/LAN8700i ...