NTD20N06L-1G ON Semiconductor, NTD20N06L-1G Datasheet - Page 5

• Manufacturer Part Number: NTD20N06L-1G
• Description: MOSFET N-CH 60V 20A IPAK
• Manufacturer: ON Semiconductor

Specifications of NTD20N06L-1G

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 48 mOhm @ 10A, 5V
• Drain To Source Voltage (vdss): 60V
• Current - Continuous Drain (id) @ 25° C: 20A
• Vgs(th) (max) @ Id: 2V @ 250µA
• Gate Charge (qg) @ Vgs: 32nC @ 5V
• Input Capacitance (ciss) @ Vds: 990pF @ 25V
• Power - Max: 1.36W
• Mounting Type: Surface Mount
• Package / Case: IPak, TO-251, DPak, VPak (3 straight leads + tab)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
power averaged over a complete switching cycle must not
exceed (T
in switching circuits with unclamped inductive loads. For
DM
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
A Power MOSFET designated E−FET can be safely used
5
4
3
2
1
6
0
) nor rated voltage (V
0
Figure 8. Gate−To−Source and Drain−To−Source
J(MAX)
Q
1
r
4
,t
Voltage versus Total Charge
Q
− T
f
) do not exceed 10 ms. In addition the total
G
, TOTAL GATE CHARGE (nC)
C
)/(R
qJC
8
Q
T
).
DSS
Q
2
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
) is exceeded and the
20
16
12
8
4
0
12
Figure 10. Diode Forward Voltage versus Current
0.6
V
T
V
J
GS
SD
= 25°C
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
= 0 V
0.68
I
T
D
16
V
SAFE OPERATING AREA
J
C
GS
= 20 A
= 25°C
) of 25°C.
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NTD20N06L
0.76
20
5
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
equal the values indicated.
1000
100
0.84
Although many E−FETs can withstand the stress of
10
1
1
V
I
V
D
DS
GS
= 20 A
DM
= 30 V
= 5 V
t
0.92
t
Figure 9. Resistive Switching Time
d(off)
d(on)
Variation versus Gate Resistance
), the energy rating is specified at rated
t
t
R
r
f
G
, GATE RESISTANCE (OHMS)
D
), in accordance with industry custom.
1
10
D
can safely be assumed to
100