SI3201-FSR Silicon Laboratories Inc, SI3201-FSR Datasheet
SI3201-FSR
Specifications of SI3201-FSR
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SI3201-FSR Summary of contents
Page 1
... DTMF and caller ID generation, and a comprehensive set PK of telephony signaling capabilities including expanded support of Japan and China country requirements. The ProSLIC is packaged in a 38-pin QFN and TSSOP, and the Si3201 high-voltage line interface device is packaged in a thermally-enhanced 16-pin SOIC. Functional Block Diagram INT ...
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Si3216 2 Rev. 1.0 ...
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... Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 5. Pin Descriptions: Si3216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7. Ordering Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11 ...
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... C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3216 DDD DDA1 DDA2 IND STG JA Si3201 BAT V INHV STG 3 Rev. 1.0 Value Unit –0.5 to 6.0 V ±10 mA –0 ...
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... Ambient Temperature Si3216 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
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Si3216 Table 3. AC Characteristics—Wideband Audio Mode: Si3216 ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter TX/RX Performance—Wideband Audio Mode Overload Level ...
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Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Noise Performance—Wideband Audio Mode 3 Idle ...
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Si3216 (dB 100 –1 –4.5 Figure 1. Transmit and Receive Path Attenuation Distortion—Wideband Mode (ms 0.25 50 100 Figure 2. Transmit and Receive Path Group Delay Distortion—Wideband Mode 8 6.4k 7k 300 4k 6.4k Rev. ...
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Table 4. AC Characteristics—Narrowband Audio Mode ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter TX/RX Performance—Narrowband Audio Mode Overload Level 1 Single ...
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... RX and TX 3.4 kHz 200 Hz–3.4 kHz, Q1,Q2 150, 1% mismatch 240 5 Q1,Q2 300 to 800 5 Q1,Q2 Using Si3201 200 Hz–3.4 kHz 200 Hz–3.4 kHz at TIP or RING Register selectable ETBO/ETBA Active off-hook 200 Hz–3.4 kHz Register selectable ETBO/ETBA ...
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Figure 3. Transmit and Receive Path SNDR—Narrowband Mode Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 4. Overload Compression Performance Rev. 1.0 Acceptable Region 3 4 ...
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Si3216 Figure 5. Transmit Path Frequency Response—Narrowband Mode 12 Typical Response Typical Response Rev. 1.0 ...
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Figure 6. Receive Path Frequency Response—Narrowband Mode Rev. 1.0 Si3216 13 ...
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Si3216 Figure 7. Transmit Group Delay Distortion—Narrowband Mode Figure 8. Receive Group Delay Distortion—Narrowband Mode 14 Rev. 1.0 ...
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Table 5. Linefeed Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range R LOOP DC Loop Current Accuracy ...
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Si3216 Table 6. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...
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... BAT Sleep (RESET = 0) BAT Open (DCOF = 1) Active on-hook ETBO = Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA LIM Ground-start Ringing PK_RING PK sinewave ringing, REN = 1 When using Si3201 x V BAT BAT Rev. 1.0 Si3216 1 2 Max Typ Typ 0.1 0.13 0 ...
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Si3216 Table 10. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: ...
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SCLK t su1 CS SDI t d1 SDO Table 12. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK ...
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... Table 18 or from App Note 45. R21 2. Only one component per system needed All circuit ground should have a single-point connection to the ground plane. 1 R29 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. Figure 11. Si3216(M) Application Circuit Using Si3201 ...
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... Table 13. Si3216(M) + Si3201 External Component Values Component (s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 C18,C19 4.7 µF Ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30, C31 10 µ Electrolytic, ±20% ...
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Si3216 Q1 Q4 5401 5401 R10 10 TIP Q6 5551 C8 R13 C5 220nF 5.1k 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 18 or from “AN45: ...
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Table 14. Si3216(M) External Component Values (Continued) 200 k , 1/10 W, 1% R1,R3 100 k , 1/10 W, 1% R2,R4,R5, R102,R104,R105 80.6 , 1/4 W, 1% R6,R7 4.7 k , 1/10 W, ...
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Si3216 Table 15. Si321x BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10* C14* C25* R16 R17 1/10 W, ±5% (See “AN45: Design Guide for The Si3210 DC- DC Converter” or Table 20 for value ...
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Table 16. Si321xM MOSFET/Transformer DC-DC Converter Component Values Component ( µF, 100 V, Electrolytic, ±20% C14* C25* 10 µF, Electrolytic, ±20% C27 470 pF, 100 V, X7R, ±20% R17 R18 1/4 W, ±5% (See DC Converter” R19,R20 1/10 ...
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... C7,C8 3.0 k , 1/10 W, 5% R23,R24 The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For this optional subcircuit, C7 and C8 are different in voltage and capacitance to the standard circuit. R23 and R24 are additional components. ...
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... FSK (caller ID) signaling, and call progress tones. Pulse metering signal generation is also integrated. The Si3201 linefeed interface IC performs all high-voltage functions option, the Si3201 can be replaced with low-cost discrete components. The linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage ...
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... Si3216 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. ...
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... A/D D/A AC Control AC Sense Control Loop TIP or RING Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 22. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing ...
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... Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. 2.1.5. Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor ...
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... Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC device uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). ...
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... Loop Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input Signal Processor when the ProSLIC is in the On-Hook Transmission or On-Hook Active Linefeed state, as indicated by the Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a ...
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... Calibration should be performed in the On-Hook state. RING or TIP must not be connected to ground during the calibration. When using the Si3201, automatic calibration routines for RING gain mismatch and TIP gain mismatch should not be performed. Instead of running these two calibrations automatically, consult “AN35: Si321x User’s Quick Reference Guide” ...
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... T1 specified in “AN45: Design Guide for the Si3210/15/16 DC-DC Converter” and includes several taps on the primary side to facilitate a wide range of input voltages. The “M” version of the ProSLIC must be used for the application circuit depicted in Figure 14 on page 24 because the DCFF pin is used to drive M1 directly and, therefore, must be the same polarity as DCDRV. DCDRV is not used in this circuit option ...
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... BATH Low Battery Voltage—V BATL V OV Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31 LIM ...
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... Figure 20. Simplified Tone Generator Diagram 36 described above. 2.3. Tone Generation Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single or dual tone frequency and amplitude combinations and spare the user the effort of generating the required POTS signaling tones on the PCM highway ...
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Oscillator Frequency and Amplitude Each of the two-tone generators contains a two-pole resonant oscillator circuit with frequency and amplitude. These two-tone generators are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the ...
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Si3216 Table 28. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude ...
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... When the Ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC goes into the Ringing state and starts the first ring. At the expiration of RAT, the ProSLIC turns off the ringing waveform and goes to the on-hook transmission state. Upon expiration of RIT, ringing again initiates. This ...
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... Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... V TIP-RING V ROFF T=1/freq t RISE Figure 22. Trapezoidal Ringing Waveform To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations: 1 RNGY -- - Period = 2 Desired V PK ----------------------------------- RNGX = 96 V ...
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... Sense (LCS) value provided by the current monitoring OVR circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the Ringing state as indicated by the )/2, is fixed. This Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection ...
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... Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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Si3216 44 Rev. 1.0 ...
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... The transhybrid balance can also be disabled, if desired, using the appropriate register setting. 2.5.5. Loopback Testing Four loopback test options are available in the ProSLIC: The full analog loopback (ALM2) tests almost all the circuitry of both the transmit and receive paths. The transmit data stream is fed back serially to the input of the receive path expander ...
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... While the interrupt status registers are non-zero, the INT pin will remain asserted. 2.9. Serial Peripheral Interface The control interface to the ProSLIC is a 4-wire interface modeled after commonly-available microcontroller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO) ...
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... SDI is a “don’t care” during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin remains high-impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge ...
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Si3216 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...
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... PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4 and 5) registers ...
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Si3216 Table 32. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Table 33. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: ...
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... Rev. 1.0 Bit 3 Bit 2 Bit 1 Bit 0 RNI[3:0] PCMT GCI TRI TXS[9:8] RXS[9:8] ALM2 DLM ALM1 ATX[1:0] ARX[1:0] TISE TISS[2:0] HYBA[2:0] PFR BIASOF SLICOF DACON GMM GMON O2IP O2AP O1IP O1AP Q2AP Q1AP LCIP RTIP INDP O2IE O2AE O1IE O1AE Q2AE Q1AE LCIE ...
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... OZ1 O1TAE OSS2 OZ2 O2TAE RSS RDAC RTAE OAT1[7:0] OAT1[15:8] OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE VOV MNCM MNDIF SPDS Rev. 1.0 Si3216 Bit 3 Bit 2 Bit 1 Bit 0 IAS O1TIE O1E O1SO[1:0] ...
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Si3216 Table 34. Direct Register Summary (Continued) Register Name 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High ...
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Table 34. Direct Register Summary (Continued) Register Name 96 Calibration Control/ Status Register 1 97 Calibration Control/ Status Register 2 98 RING Gain Mismatch Calibration Result 99 TIP Gain Mismatch Calibration Result 100 Differential Loop Current Gain Calibration Result 101 ...
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Si3216 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...
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Register 1. PCM Mode Select Bit D7 D6 Name PNI2 WBE PCME Type R R/W R/W Reset settings = 1000_1000 Bit Name 7 PNI2 Part Number Identification 2. Note: PNI[2:0] can be read in direct Register Si3210, ...
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Si3216 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission ...
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Register 5. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC ...
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Si3216 Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 24 on page 44 Full analog loopback ...
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Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP TXM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF ...
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Si3216 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type R/W Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB ...
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... Reserved Read returns zero. 1 BIASOF DC Bias Power-Off Control Automatic power control Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control Automatic power control Override automatic control and force SLIC circuitry off DCOF PFR R/W R/W Function Rev. 1.0 ...
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Register 15. Powerdown Control 2 Bit D7 D6 Name ADCM Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual ...
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Si3216 Register 18. Interrupt Status 1 Bit D7 D6 Name RGIP Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. ...
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Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3216 Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request ...
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Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read/write bit with no function. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. ...
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Si3216 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE ...
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Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved Read/write ...
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Si3216 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA ...
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Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register ...
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Si3216 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL OZ1 Type R R/W R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 ...
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Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 OZ2 Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns ...
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Si3216 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 ...
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Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type ...
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Si3216 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...
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Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type ...
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Si3216 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, ...
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Si3216 Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual ...
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Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH CBY Type R/W R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins ...
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Si3216 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (See Figure 19 on page 35.) This bit selects the programmable range ...
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Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...
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Si3216 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. The state of this bit reflects the real time ...
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Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady ...
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Si3216 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage ...
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Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. V equal to V ...
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Si3216 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of ...
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Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (V ...
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Si3216 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range ...
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Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage ground. ...
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Si3216 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real time current through Q3. The range (0x00) to ...
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Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real time current through Q6. The range (0x00) to 80.58 ...
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Si3216 Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 (Si3216) Reset settings = 0011_0100 (Si3216M) Bit Name 7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to ...
Page 97
... Calibration enabled or in progress. 3 CALT TIP Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult “AN35: Si321x User’s Quick Reference Guide” and follow the instructions for manual calibration Normal operation or calibration complete Calibration enabled or in progress. ...
Page 98
Si3216 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1110 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled ...
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Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration ...
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Si3216 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result ...
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Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ...
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Si3216 Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the ...
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Bit Name 1 DCFIL DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter con- trol loop Voice band squelch disabled Voice band squelch enabled. 0 HYSTEN Loop Closure ...
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Si3216 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect ...
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Table 36. Oscillator Indirect Registers Summary (Continued) Addr. D15 D14 D13 D12 D11 Table 37. Oscillator Indirect Registers Description Addr. 0 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 1 Oscillator 1 Amplitude Register. Sets tone ...
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Si3216 Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. 13 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively mul- tiplied by DACG to achieve gain/attenuation. A value ...
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... VCMR[3:0] 64 VMIND[3:0] 66 LCRTL[5:0] Table 41. SLIC Control Indirect Registers Description Addr. 15 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hys- teresis is enabled (direct Register 108, bit 0). The range is 0– 1.27 mA steps. 16 Ring Trip Threshold. ...
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... Si3216 Table 41. SLIC Control Indirect Registers Description (Continued) Addr. 19 Power Alarm Threshold for Transistors Q1 and Q2. 20 Power Alarm Threshold for Transistors Q3 and Q4. 21 Power Alarm Threshold for Transistors Q5 and Q6. 22 Loop Closure Filter Coefficient. 23 Ring Trip Filter Coefficient. 24 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. ...
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FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL ...
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Si3216 5. Pin Descriptions: Si3216 QFN DTX FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...
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... Capacitor used in low pass filter to stabilize SLIC feedback loops QGND Component Reference Ground CAPM SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops STIPDC TIP Sense. Analog current input used to sense voltage on the TIP lead SRINGDC RING Sense. ...
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Si3216 Pin # Pin # Name QFN TSSOP 24 28 ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog current output driving Q4 VDDD Digital Supply Voltage. Digital power ...
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... Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I RING I/O 4 VBAT 5 VBATH 7 GND 8 VDD 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side Exposed Pad TIP 1 16 ITIPP ITIPN RING 3 14 IRINGP 4 13 IRINGN VBAT VBATH STIPE GND ...
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... ProSLIC Si3201-KS Linefeed Interface Si3201-BS Linefeed Interface Si3201-FS Linefeed Interface Si3201-GS Linefeed Interface Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 114 Table 44. Device Ordering Guide DCFF Pin Package Output DCDRV QFN-38 ...
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... Eval Board, Daughter Card Daughter Card Only Daughter Card Only Eval Board, Daughter Card Eval Board, Daughter Card Daughter Card Only Daughter Card Only Rev. 1.0 Si3216 Linefeed Interface Discrete Si3201 Discrete Si3201 Discrete Si3201 Si3201 Discrete Discrete Si3201 Discrete Si3201 115 ...
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Si3216 8. Package Outline: 38-Pin QFN Figure 30 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the illustration. Figure 30. 38-Pin Quad Flat No-Lead Package (QFN) Table 46. Package Diagram Dimensions ...
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Package Outline: 38-Pin TSSOP Figure 31 illustrates the package details for the Si321x. Table 47 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C Figure ...
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... Si3216 10. Package Outline: 16-Pin ESOIC Figure 32 illustrates the package details for the Si3201. Table 48 lists the values for the dimensions shown in the illustration . –A– Seating Plane Figure 32. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 48. Package Diagram Dimensions ...
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... AN34: Si321x Hardware Reference Guide AN35: Si321x User’s Quick Reference Guide AN39: Connecting the ProSLIC to the W & G PCM-4 AN45: Design Guide for the Si321x DC-DC Converter AN46: Demonstration Software Guide for the Si3210 DC-DC Converter ...
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Si3216 OCUMENT HANGE IST Revision 0.61 to Revision 0.9 Separated the Si3216/15 document into two data sheets. Added Quad Flat No-Lead (QFN) package. Removed references to Si3215. Updated Figure 11 on page 20. ...
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N : OTES Rev. 1.0 Si3216 121 ...
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