MT90863AG Zarlink, MT90863AG Datasheet
MT90863AG
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MT90863AG Summary of contents
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... DS CS R/W Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved Rate Conversion Digital Switch MT90863AL MT90863AG MT90863AL1 MT90863AG2 Applications • Medium and large switching platforms • CTI application • Voice/data multiplexer • ...
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... The MT90863 also offers a sub-rate switching configuration which allows 2-bit wide 16 kb/s data channels to be switched within the device. The device has features (such as: message mode; input and output offset delay; direction control; and, high impedance output control) that are programmable on per-stream or per-channel basis. MT90863 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Connection Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 Local Connection Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 Initialization of the MT90863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 JTAG Support 7.1 Test Access Port (TAP 7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 Test Data Register MT90863 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure Bus Timing for Stream rate of 2.048, 4.096 or 8.192 Mb Figure 13 - HMVIP Bus Timing for Stream rate of 2.048 Mb/s or 8.192 Mb Figure 14 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15 - Output Driver Enable (ODE Figure 16 - Motorola Non-Multiplexed Bus Timing MT90863 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 19 - Local Connection Memory Low Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 20 - LSAB Bits Programming for Different Local Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 21 - LCAB Bits Programming for Different Data Rates Table 22 - Local Connection Memory High Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 23 - Boundary Scan Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MT90863 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... VSS VDD 127 STio24 MT90863 128 Pin MQFP 28mm x 28mm Pin Pitch 0.80mm Figure 2 - MQFP Pin Connections 6 Zarlink Semiconductor Inc. Data Sheet STi13 STi12 63 STi11 STi10 61 STi9 STi8 59 STi7 STi6 57 STi5 STi4 55 STi3 STi2 53 STi1 STi0 51 VDD VSS 49 DTA D15 ...
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... G A0 VSS IC2 VDD L CS R/W VSS corner is identified by metallized markings. Figure 3 - BGA Pin Connections Zarlink Semiconductor Inc. MT90863 STio19 STio17 STio15 STio14 STio11 STio8 STio6 STio20 STio18 STio16 STio13 STio10 STio7 STio5 STio21 VDD VSS STio12 STio9 VDD VSS VSS ...
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... Test Mode Select (3.3 V Input with internal pull-up): JTAG signal that controls the state transitions of the TAP controller. Test Serial Data In (3.3 V Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin. 8 Zarlink Semiconductor Inc. Data Sheet Description ...
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... In 8 Mb/s mode, these inputs accept data rates of 8.192 Mb/s with 128 channels per stream. Serial Input Streams Tolerant Inputs Mb/s or Sub- rate Switching mode, these inputs accept data rates of 2.048 Mb/s with 32 channels per stream. 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s or 8.192 Mb/s. By using Zarlink’s message mode capability, the microprocessor can access input and output time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST- BUS devices ...
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... Mb/s. When 8 Mb/s mode is enabled, STio0 to STio15 have a data rate of 8.192 Mb/s. When HMVIP mode is enabled, STio0 to STio15 have a data rate of 2.048 Mb/s and STio16 to STio23 have a data rate of 8.192 Mb/s. Table 2 describes the data rates and mode selection for the backplane interface. MT90863 11 Zarlink Semiconductor Inc. Data Sheet ...
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... STi/STo (2Mb/s mode) STi12/STo12 0 1 (Sub-rate Switching) Figure Bus Mode Timing for 2, 4 and 8 Mb/s Data Streams MT90863 Channel Channel Channel 0 6 Channel Zarlink Semiconductor Inc. Data Sheet Channel 127 Channel Channel Channel 127 1 0 Bit 1 Channel 127 Channel Channel 31 1 ...
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... The frame output offset registers (FOR0 & FOR1) control the output offset delays for each backplane output stream via the OFn bit programming. Table 12 and Figure 10 detail frame output offset programming. MT90863 Channel Channel Channel Zarlink Semiconductor Inc. Data Sheet Channel Channel 127 Channel 127 1 0 ...
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... STio0 - 31 STio0 - 31 STio0 - 31 STio0 - 31 STio0 - 15 STio16 - 31 STio0 - 15 STio16 - 31 HMVIP Mode STio0 - 15 STio16 - 23 STio24 - 31 14 Zarlink Semiconductor Inc. Data Sheet HMVIP Mode 244 ns 4.096 MHz Data Rate 2.048 Mb/s 2.048 Mb/s 4.096 Mb/s 4.096 Mb/s 8.192 Mb/s Not available 8.192 Mb/s Not available 2 ...
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... Sub-rate Switching Input Stream at 2.048 Mb/s STi13 - 15 Not available STo0 - 11 2.048 Mb/s STo12 Sub-rate Switching Output Stream at 2.048 Mb/s STo13 - 15 Not available STi0 - 3 8.192 Mb/s STi4 - 15 Not available STo0 - 3 8.192 Mb/s STo4 - 15 Not available 15 Zarlink Semiconductor Inc. Data Sheet Data Rate ...
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... Memory Block Programming section). The memory select bits control the selection of the connection memory or the data memory. The stream address bits define an internal memory subsections corresponding to serial input or serial output streams. MT90863 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Input Offset Selection Register 4, DOS4 Input Offset Selection Register 5, DOS5 Frame Output Offset Register, FOR0 Frame Output Offset Register, FOR1 Address Buffer Register, ABR Data Write Register, DWR Data Read Register, DRR Table 4 - Address Memory Map 17 Zarlink Semiconductor Inc. Data Sheet Location Note 2) ( ...
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... Change the RS bit in the ABR register from low to high to initiate the data transfer from the memory to the DRR register. After several master clock cycles, the CDA bit in the ABR register changes MT90863 126 127 Zarlink Semiconductor Inc. Data Sheet Location Note 3) ( ...
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... Enable 1 Enable , Reset Value: 0000 . MBP MS2 MS1 MS0 Description Table 6 - Control (CR) Register Bits 19 Zarlink Semiconductor Inc. Data Sheet STo0-15 OE bit in Local CM Output Driver Status 0 Per Channel High Impedance Don’t care High Impedance 1 Enable 1 Enable STA4 STA3 STA2 STA1 STA0 ...
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... Mb/s ST-BUS Mode 2 Mb/s Sub-rate Switching Mode 8 Mb/s ST-Bus Mode Backplane Switching Mode 2 Mb/s ST-BUS Mode 2 Mb/s CT Bus Mode 4 Mb/s ST-BUS Mode 4 Mb/s CT Bus Mode 8 Mb/s ST-BUS Mode 8 Mb/s CT Bus Mode HMVIP Mode 20 Zarlink Semiconductor Inc. Data Sheet STA4 STA3 STA2 STA1 STA0 ...
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... When this process is complete, the microprocessor controlling the matrices can either bring the ODE pin high or enable the OSB bit in IMS register to relinquish the high impedance state control. MT90863 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Set this bit to zero for at least one frame (125 µs) to start another frame evaluation. Table 8 - Internal Mode Selection (IMS) Register Bits MT90863 , BBPD BBPD LBPD LBPD BBPD Description STio0 - 31, STo0 - High impedance state 0 1 Enable 1 1 Enable X 0 Per-channel high impedance 22 Zarlink Semiconductor Inc. Data Sheet LBPD LBPD BPE OSB SFE 1 0 ...
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... These bits are reset to zero when the SFE bit of the IMS register changes from (FD8 = MSB, FD0 = LSB). These bits are also read-only Table 9 - Frame Alignment (FAR) Register Bit MT90863 , CFE FD9 FD8 FD7 FD6 FD5 Description 23 Zarlink Semiconductor Inc. Data Sheet FD4 FD3 FD2 FD1 FD0 ...
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... ST-BUS F0i C16i Offset Value 0 1 FEi Input C4i HMVIP F0i C16i Offset Value FEi Input Figure 8 - Example for Frame Alignment Measurement MT90863 (FD[8: (FD9 = 0, sample at CLK low phase (FD[8: (FD9 = 1, sample at CLK high phase) 24 Zarlink Semiconductor Inc. Data Sheet ...
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... IF220 DLE22 IF212 IF211 IF210 DOS5 register Description DLEn =0, if clock rising edge is at the 3/4 point of the bit cell. DLEn =1, if clock falling edge is at the 3/4 point of the bit cell. 25 Zarlink Semiconductor Inc. Data Sheet DLE1 IF02 IF01 IF00 ...
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... IF140 DLE14 IF132 IF131 IF130 DOS3 register IF181 IF180 DLE18 IF172 IF171 IF170 DOS4 register IF221 IF220 DLE22 IF212 IF211 IF210 DOS5 register Description 26 Zarlink Semiconductor Inc. Data Sheet IF10 DLE1 IF02 IF01 IF00 DLE0 DLE5 IF42 IF41 IF40 DLE4 IF90 ...
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... MT90863 Measurement Result from Frame Delay Bits FD9 FD2 FD1 FD0 Bit 7 Bit 7 Bit 7 Bit 7 27 Zarlink Semiconductor Inc. Data Sheet Corresponding Offset Bits IFn2 IFn1 IFn0 DLEn offset=0, DLE=0 offset=1, DLE=0 offset=0, DLE=1 offset=1, DLE=1 denotes the 3/4 point of the bit cell ...
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... FOR registers OF10 OF09 OF08 OF07 OF06 OF05 FOR0 register OF23 OF22 OF21 FOR1 register Description Bit 7 Bit 7 Bit 7 Bit 7 28 Zarlink Semiconductor Inc. Data Sheet OF04 OF03 OF02 OF01 OF00 OF20 OF19 OF18 OF17 OF16 offset=0 offset=1 offset=0 offset=1 ...
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... Table 14 - Data Write (DWR) Register Bits MT90863 for ABR register CA5 CA4 CA3 CA2 CA1 CA0 Description for DWR register WR10 WR9 WR8 WR7 WR6 WR5 Description 29 Zarlink Semiconductor Inc. Data Sheet SA4 SA3 SA2 SA1 SA0 WR4 WR3 WR2 WR1 WR0 ...
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... BCAB6 - BCAB0) are output on the output channel and stream associated with this location. Table 16 - Blackplane Connection Memory Bits MT90863 for DRR register RD10 RD9 RD8 RD7 RD6 RD5 Description BCAB BSAB BSAB BSAB BSAB BCAB Description 30 Zarlink Semiconductor Inc. Data Sheet RD4 RD3 RD2 RD1 RD0 BCAB BCAB BCAB BCAB BCAB ...
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... BCAB6 to BCAB0 (128 channel/frame) BCAB4 to BCAB0 (32 channel/frame) BCAB6 to BCAB0 (128 channel/frame LCAB LSAB LSAB LSAB LCAB LCAB Description STio0-31 (backplane, 2 Mb/s mode) STio0-31 (backplane, 4 Mb/s mode) STio0-15 (blackplane, 8 Mb/s mode) STio0-23 (blackplane, HMVIP mode) 31 Zarlink Semiconductor Inc. Data Sheet LCAB LCAB LCAB LCAB ...
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... LCAB Bits Used to Determine the Source Channel of the Connection LCAB4 to LCAB0 (32 channel/frame) LCAB5 to LCAB0 (64 channel/frame) LCAB6 to LCAB0 (128 channel/frame) LCAB4 to LCAB0 (32 channel/frame) LCAB6 to LCAB0 (128 channel/frame) LCAB4 to LCAB0 (32 channel/frame) LCAB6 to LCAB0 (128 channel/frame) 32 Zarlink Semiconductor Inc. Data Sheet LCAB LCAB LCAB ...
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... MT90863 Description Bit7-6 will be the output of the subrate switching stream Bit5-4 will be the output of the subrate switching stream Bit3-2 will be the output of the subrate switching stream Bit1-0 will be the output of the subrate switching stream 33 Zarlink Semiconductor Inc. Data Sheet LSR1 LSR0 ...
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... The MT90863 scan register contains 212 bits. Bit 0 in Table 23 Boundary Scan Register is the first bit clocked out. All tri-state enable bits are active high. Device Pin MT90863 LSB Boundary Scan Bit 0 to Bit 213 Tri-state Output Control Scan Cell R/W CS Table 23 - Boundary Scan Register Bits 34 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell ...
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... STo9 95 96 STo10 97 98 STo11 99 100 STo12 101 102 STo13 103 104 STo14 105 106 STo15 107 108 C16i F0i C4i/C8i F0o 112 113 C4o 114 115 Table 23 - Boundary Scan Register Bits (continued) 35 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell ...
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... STio28 200 201 STio29 203 204 STio30 206 207 STio31 209 210 RESET Table 23 - Boundary Scan Register Bits (continued) 36 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell 118 121 124 127 130 133 136 139 142 145 148 151 154 ...
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... Sym. Level Units Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.5 5.0 V -0 -0 ° +125 Max. Units Test Conditions °C +85 3 5 Units Test Conditions mA Output unloaded µA 0≤<V≤V See DD µ ...
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... HCH 61 t HCL t 244 HFPW t 50 150 HFPS t 50 150 HFPH t 244 HCP t 122 HCH t 122 HCL - DIF - DC4O 38 Zarlink Semiconductor Inc. Data Sheet Notes ns ST-BUS mode ST-BUS, CT Bus or HMVIP mode Bus mode HMVIP mode HMVIP or CT Bus mode ns ns ...
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... FPoH t C4L t DC4o SOD8 Bit 0, Ch 127 Bit Bit SIS8 SIH8 Bit 0, Ch 127 Bit Bit SOD4 Bit SIS4 SIH4 Bit Bit SOD2 Bit Bit Bit Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =200pF =1K, C =200pF, See Note C4P t C4H ...
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... CH CFPS CFPH t t C8P C8H t FPoW t C4P t t C4H C4L SOD8 Bit Bit Bit SIS8 SIH8 Bit Bit Bit SOD4 Bit Bit SIS4 SIH4 Bit SOD2 Bit SIS2 Bit Zarlink Semiconductor Inc. Data Sheet C8L Bit Bit Bit Bit SIH2 V TT ...
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... MT90863 t HFPH t HCP t t HCH HCL FPoW FPoH t C4P t t C4H C4L SOD8 Bit Bit Bit SIS8 SIH8 Bit Bit Bit SOD2 Bit SIS2 Bit HiZ HiZ Valid Data TT 41 Zarlink Semiconductor Inc. Data Sheet C8L Bit Bit Bit SIH2 V TT ...
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... Figure 15 - Output Driver Enable (ODE) Sym. Min. t CSS t RWS t ADS t CSH t RWH t ADH t DDR_REG t DDR_MEM t DHR t DSW_REG t SWD t 5 DHW t AKD_REG t AKD_MEM t AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Test Typ. Max. Units Conditions =50pF L 16 440 =50pF =1K L ...
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... DS CS R/W A0-A7 D0-D15 READ D0-D15 WRITE DTA Figure 16 - Motorola Non-Multiplexed Bus Timing MT90863 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD 43 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW AKH ...
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... Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE ACN 213935 20Jan03 DATE APPRD. Package Code : GA Previous package codes: ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...