ZL30106QDG Zarlink, ZL30106QDG Datasheet
ZL30106QDG
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ZL30106QDG Summary of contents
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... RST HMS MODE_SEL1:0 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved. ZL30106QDG1 64 pin TQFP* Trays, Bake & Drypack • Provides lock, holdover and accurate reference fail indication • Selectable loop filter bandwidth 922 Hz • ...
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... It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs. The ZL30106 output clocks wander and jitter generation are compliant with the associated transport medium specifications. ZL30106 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ZL30106 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL30106 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 23 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24 - REF_SYNC0/1 Timing Figure Output Timing Referenced to F8/F32o Figure 26 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 27 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 28 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ZL30106 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Table “DC Electrical Characteristics*“ 43 Table “Performance Characteristics* - Functional“ ZL30106 Change Leaded part number ZL30106QDG has been obsoleted and replaced by ZL30106QDG1. Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note ...
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... Changed 200 "HMS=0" section Corrected time-constant of example reset circuit Corrected package power rating Corrected current consumption Corrected Schmitt trigger V levels t- Corrected output voltage note to reflect two pad strengths Updated Min. Max. values Corrected pulse widths Changed jitter numbers 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30106 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30106 does not use the e-Pad TQFP. ZL30106 ZL30106 Zarlink Semiconductor Inc. Data Sheet 34 C1.5o 32 C3o C6/8.4/34/44o OUT_SEL0 28 OUT_SEL1 OUT_SEL2 APP_SEL1 24 GND ...
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... MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of operation, see Table 4 on page 22. 18 MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description. ZL30106 Description nominal this pin is not used then it should be DD nominal DC nominal this pin is not used then it should be left DD 9 Zarlink Semiconductor Inc. Data Sheet . If DD ...
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... Multi Frame Pulse (Output). This kHz 51 ns active high framing pulse, which marks the beginning of a multi frame. 39 C19o Clock 19.44 MHz (Output). This output is used in SONET/SDH applications. 40 AGND Analog Ground AGND Analog Ground ZL30106 Description nominal DC nominal DC nominal DC nominal DC nominal DC 10 Zarlink Semiconductor Inc. Data Sheet ...
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... In the Automatic mode of operation, REFSEL0 is an output indicating which of the input references is the being selected, see Table 6 on page 26. This pin is internally pulled down to GND. 54 REF_SEL1 Reference Select 1 (Input/Output). See REF_SEL0 pin description. ZL30106 Description nominal DC nominal DC 11 Zarlink Semiconductor Inc. Data Sheet ...
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... REF_SYNC input. This feature supports the implementation of line card clocks where the line card locks to the backplane clock with a filter suitable for good tracking (high bandwidth) yet still provides a (multi) frame locked to the backplane (multi) frame. ZL30106 Description nominal DC 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 4 where REF0 experiences disruptions while REF1 is stable. ZL30106 OR REF_OOR OR dis/re-qualify timer OR REF_OOR = reference out of range. REF_DIS= reference disrupted. Both are internal signals. Figure 3 - Reference Monitor Circuit 13 Zarlink Semiconductor Inc. Data Sheet REF_FAIL0 / REF_FAIL1 / REF_FAIL2 Reference select REF_SEL1:0 state machine REF_DIS Mode select HOLDOVER state machine ...
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... C20: 20 MHz master oscillator clock Figure 5 - Out-of-Range Thresholds for APP_SEL1:0=00 ZL30106 SCM or CFM failure 200 ms REF0 C20 - C20 32 -51 -32 C20 - -50 - Zarlink Semiconductor Inc. Data Sheet REF1 Out of Range In Range 83 Out of Range In Range 96 115 Out of Range In Range Frequency offset [ppm] 100 75 ...
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... C20 -4.6 4.6 7.4 - C20 -52 - C20 - -20 20 C20 20 -60 -20 32 -50 - Zarlink Semiconductor Inc. Data Sheet Out of Range In Range Out of Range In Range 16.6 Out of Range In Range Frequency offset [ppm] Out of Range In Range Out of Range In Range Out of Range In Range Frequency offset [ppm] 100 . ...
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... TIE_CLR can be kept low continuously. In that case the output clocks will always align with the selected input reference. This is illustrated in Figure 9. ZL30106 REF_SYNC Ratio to DPLL Monitor REF_SYNC Frequency Detector Figure 8 - REF_SYNC Monitor Circuit 16 Zarlink Semiconductor Inc. Data Sheet ...
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... This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30106 is always hitless unless TIE_CLR is kept low continuously. ZL30106 TIE_CLR = 1 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock 17 Zarlink Semiconductor Inc. Data Sheet ...
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... Phase = 0.01 ppm holdover_drift - Phase = mode_change - Phase = ns) = 330 ns 10 changes ZL30106 HMS = 1 Normal mode REF Output Clock Phase drift in Holdover mode REF Output Clock Return to Normal mode REF Output Clock TIE_CLR=0 REF Output Clock 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Hz. ZL30106 Lock Detector Digitally Limiter Loop Filter Controlled Oscillator State Select from Control State Machine Figure 11 - DPLL Block Diagram 19 Zarlink Semiconductor Inc. Data Sheet LOCK DPLL Reference to Frequency Synthesizer Feedback signal from Frequency Select MUX Feedback frame pulse; F8o or F2ko ...
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... As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30106 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30106 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30106 20 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz 2 kHz 8 kHz 1 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz 21 Zarlink Semiconductor Inc. Data Sheet Out Of Range Limits ppm 9 ppm ppm ppm Loop Filter Phase Slope Bandwidth Limiting μ ...
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... Normal (with automatic Holdover) 1 Holdover 0 Freerun 1 Automatic (Normal with automatic Holdover and automatic reference switching) Table 4 - Operating Modes ± 32 ppm. See Applications - Section 6.2, “Master Clock“. 22 Zarlink Semiconductor Inc. Data Sheet F4o, F8o, F16o F16o, F32o, F65o ± 32 ppm output clock ...
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... ZL30106 goes into Holdover mode and returns to Normal mode through the TIE correction state regardless of the logic value on HMS pin. ZL30106 ± ± 0.1 ppm per ° °C change in temperature, while the 23 Zarlink Semiconductor Inc. Data Sheet ± 32 ppm ...
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... TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. ZL30106 Normal (HOLDOVER=0) REF_DIS=0 REF_DIS=1 REF_DIS=1 (REF_DIS=0 and HMS=1) or REF_CH=1 REF_SEL0 Input Reference Selected 0 REF0 1 REF1 0 REF2 1 REF2 Table 5 - Manual Reference Selection 24 Zarlink Semiconductor Inc. Data Sheet REF_CH=1 and (REF_SYNC failed) TIE Correction (HOLDOVER=1) ...
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... Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11) ZL30106 REF0 REF1 Lock Time RST && REF_OOR0=0 REF_OOR0=0 && REF_OOR1=1 REF0 REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0 REF_OOR0=1 && REF_OOR1=0 REF2 Reference 25 Zarlink Semiconductor Inc. Data Sheet RST && REF_OOR0=1 && REF_OOR1=0 REF1 Reference ...
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... REF_FAIL pin is de-asserted, and the REF_SEL outputs indicate that the device has remained locked to the old reference. The LOCK pin remains asserted. ZL30106 REF_SEL0 Input Reference (output pin) 0 REF0 1 REF1 Normal (HOLDOVER=0) REF_CH=1 REF_DIS=0 and REF_OOR=0 REF_DIS=1 or REF_OOR=1 TIE Correction (HOLDOVER=1) (REF_DIS=0 and REF_OOR=0 and HMS=1) or REF_CH=1 26 Zarlink Semiconductor Inc. Data Sheet ...
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... TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de- assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 17 illustrates this process. ZL30106 10 s Lock Time 27 Zarlink Semiconductor Inc. Data Sheet ...
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... F8o pulses respectively. This is illustrated in Figure 18 ST_BUS clock and frame pulse pair is used as the REF and REF_SYNC inputs, the ST-BUS frame pulse must be inverted first before it can be used as the REF_SYNC pulse. ZL30106 REF1 Lock Time 28 Zarlink Semiconductor Inc. Data Sheet ...
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... TIE correction circuit will not be activated and the PLL will align its output clock and frame pulse with the input REF and REF_SYNC pair. REF_SYNC0 kHz REF0/1 = C8o F8o C8o REF_SYNC0 kHz REF0/1 = C19o F2ko C19o Figure 18 - Examples of REF & REF_SYNC to Output Alignment ZL30106 aligned aligned 29 Zarlink Semiconductor Inc. Data Sheet ...
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... For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 μs/s. ...
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... Although a short lock time is desirable not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. ZL30106 31 Zarlink Semiconductor Inc. Data Sheet ...
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... V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178. 6.2 Master Clock The ZL30106 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30106. 6.2.1 Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered ...
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... V supply (e.g., by using a schottky diode or controlled slew rate) ZL30106 20 MHz as required fundamental parallel as required 50 Ω 20 MHz OSCi 1 MΩ OSCo 100 Ω 1 μH The 100 Ω resistor and the 1 μH inductor may improve stability and are optional. Figure 20 - Crystal Oscillator Circuit 33 Zarlink Semiconductor Inc. Data Sheet . ...
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... A simple power up reset circuit with about a 60 μs reset low time is shown in Figure 21. Resistor R only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30106 ZL30106 +3 kΩ RST kΩ Figure 21 - Power-Up Reset Circuit 34 Zarlink Semiconductor Inc. Data Sheet is for protection P ...
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... Max. Units DDS μ CORES CORE V 1.43 1. 0.80 1.10 t- μA I -105 105 Zarlink Semiconductor Inc. Data Sheet Max. Units 4 125 °C 500 Max. Units 3. °C Notes outputs loaded with All device inputs are Schmitt trigger type ...
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... Symbol Min. t 484 REF2kP t 121 REF8kP t 338 REF1.5P t 263 REF2P t 63 REF8P t 38 REF16P t 38 REF8kP t 15 REFW 36 Zarlink Semiconductor Inc. Data Sheet Notes for clock and OL frame-pulse outputs for status outputs CMOS Units 0.5 · 0.7 · 0.3 · ORF Typ ...
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... SYNC_LD 2 kHz t t SYNC_LG REFP 8 kHz t t SYNC_LG REFP t 15 SYNC_W t REFP t t SYNC_LD SYNC_LG Figure 24 - REF_SYNC0/1 Timing 37 Zarlink Semiconductor Inc. Data Sheet t REF<xx>D Max. Units Notes minimum period REFP of REF0/1 clock - minimum period REFP of REF0/1 clock ns edge used for alignment ...
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... Symbol Min. t REF2kD t -27.2 REF2k_F8D t REF8kD t REF1.5D t REF1.5_F8D t REF2D t REF2_F8D t REF8D t REF8_F8D t REF16D t 29.0 REF16_F8D t REF19D t REF19_F8D 38 Zarlink Semiconductor Inc. Data Sheet Max. Units 0 1.2 ns -26.5 ns -0.3 2.0 ns -1.2 0.2 ns -1.1 0 -0.6 0.8 ns -2.0 0.1 ns -1.0 1.8 ns -1.1 1 ...
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... F16D t 28.7 30.8 C16L t -0.5 1.5 C16D t 30.0 32.1 F32H t 14.7 15.5 C32L t -0.5 0.5 C32D t 14.7 15.5 F65L t 7.1 8.0 F65D t 7.2 8.1 C65L t -1.0 1.0 C65D t 1.1 2 1.2 2 Zarlink Semiconductor Inc. Data Sheet Units Notes outputs loaded ns with ...
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... F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30106 t C2L t F4L t C4L t C8L t C16L t C32L t C65L 40 Zarlink Semiconductor Inc. Data Sheet t F8H t C2D t F4D t C4D t C8D t F16D t F16L t C16D ...
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... C3L Sym. Min. Max. t -1.0 0.5 C19D t 25.0 25.8 C19L t 25.0 26.6 F2kD 51.1 51.8 t F2kH t 1.1 2 1.2 2 C19L t F2D 41 Zarlink Semiconductor Inc. Data Sheet Units Notes ns ns outputs loaded with C1.5D t C3D Units Notes ns ns outputs loaded ns with C19D t F2kH ...
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... C6L t -0.8 0.8 C8.4D t 58.4 59.2 C8.4L t -0.5 0.5 C34D t 13.5 14.6 C34L t -1.0 0.5 C44D t 10.4 11.2 C44L t 1.1 2 1.2 2 C44L t C34L t C8.4L t C6L 42 Zarlink Semiconductor Inc. Data Sheet Units Notes outputs loaded with C44D t C34D t C8.4D t C6D ...
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... The 20 MHz master clock oscillator -52 +52 set at 0 ppm ±9.2 to ±64 ppm frequency offset, 1.5 1.5 s HMS=1, TIE_CLR=1 and BW_SEL=0 ±64 ppm frequency offset, HMS= TIE_CLR=1 and BW_SEL=0. ±9.2 ppm frequency offset HMS=1, TIE_CLR=1 and BW_SEL=0 43 Zarlink Semiconductor Inc. Data Sheet Notes Notes ...
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... Standard Telcordia GR-1244-CORE ITU-T G.823 ITU-T G.813 44 Zarlink Semiconductor Inc. Data Sheet Notes ±40 ppm frequency offset, HMS=1, TIE_CLR=1 and BW_SEL=0 ±9.2 ppm frequency offset, HMS=1, TIE_CLR=1 and BW_SEL ±64 ppm frequency offset, HMS=1, TIE_CLR=1 and BW_SEL=1 ...
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... Jitter Generation Requirements Jitter Equivalent Limit in limit in the UI filter time domain 0. G.812 ITU-T Jitter Generation Requirements Jitter Equivalent Limit in limit in the UI filter time domain 0. Zarlink Semiconductor Inc. Data Sheet ZL30106 maximum jitter Units generation 45.3 0. 324 0. ZL30106 maximum jitter Units generation 7.92 0. ZL30106 ...
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... UI 9.65 pp G.813 conformance (Option 1 and Option 2) ITU-T G.813 Limit in Equivalent limit UI in time domain ( 6.4 ns) 0.1 UI 0.64 pp 0.5 UI 3.22 pp 0 Zarlink Semiconductor Inc. Data Sheet T1.105.03 conformance ZL30106 maximum jitter Units generation 0. 0. rms 0. ZL30106 maximum jitter generation Units 0 ...
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... AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30106 Max. [ 0.45 0.47 0.53 0.42 0.58 0.42 0.55 0.56 0.42 0.46 0.56 0.60 0.49 0.40 0.43 0.43 0.44 0.43 0.46 47 Zarlink Semiconductor Inc. Data Sheet Notes ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...