AT84CS001VTPY E2V, AT84CS001VTPY Datasheet
AT84CS001VTPY
Specifications of AT84CS001VTPY
Related parts for AT84CS001VTPY
AT84CS001VTPY Summary of contents
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... DMUXes). The DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs and is capable of tracking the ADC’s output sampling rate over all operating frequency and temperature ranges. ...
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... Block Diagram Figure 1-1. Block Diagram 2 0809E–BDC–05/09 AT84CS001 e2v semiconductors SAS 2009 ...
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... A standalone delay cell is provided. It features a typical 550 ps tuning range (± 275 ps around the center value of DACTRL analog control input). A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX. The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs. e2v semiconductors SAS 2009 )/3. ...
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... Asynchronous reset signal SLEEP Sleep mode selection signal RS DMUX ratio selection signal CLKTYPE Input clock type selection signal DRTYPE Output clock type selection signal Staggered mode selection for data STAGG outputs BIST Built-in Self Test enable AT84CS001 e2v semiconductors SAS 2009 ...
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... LOW (grounded). SLEEP, DAEN, STAGG, BIST are activated on logic LOW (10Ω grounded), and deactivated on logic HIGH (10 kΩ to ground, or tied to V Figure 3-2. Control Signal Settings 10Ω Active Low Level ('0') e2v semiconductors SAS 2009 VCCD [I0…I9] 20 [I0N…I9N] 2 CLK, CLKN ...
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... Standalone delay adjust disabled N/C 10Ω to ground 1:2 ratio 10 kΩ to ground 1:4 ratio N/C 10Ω to ground CLK mode 10 kΩ to ground CLK/2 mode N/C 10Ω to ground DR/2 mode 10 kΩ to ground DR mode N/C AT84CS001 e2v semiconductors SAS 2009 ...
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... DOR/DRDN) are used as the Data Ready signal (output clock) for each port. In this mode the additional bit is disabled. 3.4 Clock Type Selection CLKTYPE and DRTYPE Two modes for the input and output clock type can be selected by way of the CLKTYPE and DRTYPE single-ended digital inputs. e2v semiconductors SAS 2009 Input Words 8… ...
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... Signal Settings” on page and Figure 3-6 above, the CLK and DR signals are not on the same time scale. In 1:4 DMUX CLKTYPE 0 1 DRTYPE 1 0 AT84CS001 5. DMUX Input Clock Type CLK CLK/2 DMUX Output Clock Type DR DR/2 e2v semiconductors SAS 2009 ...
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... Port D Figure 3-8. Staggered Mode in 1:2 Ratio (STAGG = 0) Data Out Port A Data Out Port B DRA (AORN mode DRA (AORN) in DR/2 mode DRB (BORN mode DRB (BORN) in DR/2 mode DR (in DR mode) DR (in DR/2 mode) e2v semiconductors SAS 2009 AT84CS001 0809E–BDC–05/09 9 ...
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... During the asynchronous reset, the DMUX’ differential clock input (CLK, CLKN) should be stopped at low level (state in which e2v’s single ADC Data Ready signals are when the ADC is in reset mode). The ASYNCRST pulse should last at least 1 ns. For ASYNCRST to CLK timing see 20 ...
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... Delay Cell is enabled by the DAEN input. DAEN is activated on Logic Low (Grounded), and deactivated on Logic High (10 KΩ to ground, or tied 3.3V, or left floating). CCD Figure 3-10. Block Diagram of the Standalone Delay Cell e2v semiconductors SAS 2009 2 Delay (DAI, DAIN) (550 ps tuning range) DACTRL ...
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... V(DACTRL) (V) Vtyp, Tj max Vtyp, Tamb Vtyp, Tj min AT84CS001 1,7 1,8 1,9 2,0 2,1 e2v semiconductors SAS 2009 2,2 ...
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... This delay depends on the center position of the (CLK, CLKN) clock path in relation to the digital input data in the DMUX input data paths (I0, I0N) …(I9, I9N) and (IOR, IORN). Figure 3-13. Block Diagram of the Clock Input Delay Cell e2v semiconductors SAS 2009 -30 -20 ...
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... DR/2 1:4 1:2 DR 1:4 1:2 DR/2 1:4 1:2 DR 1:4 AT84CS001 = 3.3V, or left floating). CCD voltage should be 3.3V. 1:4 DR DR/2 125 62,5 250 125 Maximum Input Data Rate Guaranteed (Gsps) 1.8 2.2 1.0 2.0 1.2 1.2 1.0 1.2 e2v semiconductors SAS 2009 ...
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... Table 4-2. Recommended Conditions of Use Parameter Symbol Digital power supply V CCD Output power supply V PLUSD Operating temperature range T C e2v semiconductors SAS 2009 Value 3.6 3 125 - 65 to 150 Comments Min 3.15 2.375 ...
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... W (5) 1.15 1.4 (5) 2.85 3.4 LVDS 1.25 1.6 V 1.25 1.375 V 350 – mV 350 500 mV 1.425 – V 1.075 1.25 V Ω 10 0.5 V Ω Infinite V 2 × CCD e2v semiconductors SAS 2009 ...
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... Given for a differential input. 3. Assuming 100Ω termination ASIC load 4. V min and V max can never be at 1.25V at the same time when Worst case value obtained with maximum supply voltages over full temperature range. e2v semiconductors SAS 2009 Symbol Test Level Min ...
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... TR/TF 4 TR/TF 4 TOD 4 5.0 TDR 4 4.5 |TOD–TDR| 4 200 AT84CS001 Typ Max Unit GHz ps Gsps Msps 460/630 550/750 ps 460/630 550/750 ps 5.9 7.1 ns 5.5 6.7 ns 500 600 ps e2v semiconductors SAS 2009 ...
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... CLK to ASYNCRST timing is given assuming V (CLKDACLTRL See Transfer characteristic on 4. The delay cell used in both standalone delay cell and Input clock path, has a characteristics that is not linear with Junction temperature. The largest tuning range is obtained near ambient temperature. See e2v semiconductors SAS 2009 Test Symbol Level ...
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... It is highly recommended to stop the clock at the Low level when ASYNCRST is active (high level). Note that when e2v's ADCs are in reset, the ADC Data Ready output (input clock of the DMUX) is stopped at the low level. In the case where the clock can not be stopped during the reset (not recommended not allowed to have an active edge (rising edge in CLK mode but both rising and falling edge in CLK/2 mode) of the CLK clock within a ± ...
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... Timing Diagrams Figure 4-2. Simultaneous 1:2 Mode – CLKTYPE = DR/2 – DRTYPE = DR Figure 4-3. Simultaneous 1:4 Mode – CLKTYPE = DR/2 – DRTYPE = DR e2v semiconductors SAS 2009 AT84CS001 21 0809E–BDC–05/09 ...
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... Staggered 1:2 Mode – CLKTYPE = DR/2 – DRTYPE = DR Note: DATA_READY A = DRA (pin A6) DATA_READY B = DRB (pin H1) Figure 4-5. Staggered 1:4 Mode – CLKTYPE = DR/2 – DRTYPE = DR Note: DATA_READY A = DRA (pin A6) DATA_READY B = DRB (pin H1) DATA_READY C = DRC (pin W5) DATA_READY D = DRD (pin W16) 22 0809E–BDC–05/09 AT84CS001 e2v semiconductors SAS 2009 ...
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... Parameter is guaranteed by design and characterization testing (thermal steady-state 4 conditions at specified temperature). 5 Parameter is a typical value only. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). The level 1 and 2 tests are performed at 10 MHz. e2v semiconductors SAS 2009 AT84CS001 23 0809E–BDC–05/09 ...
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... Inverted phase (-) digital outputs for port A In-phase (+) additional bit output for port A or inverted phase (-) output clock in staggered mode for port A Inverted phase (-) additional bit output for port A or in-phase (+) output clock in staggered mode for port A e2v semiconductors SAS 2009 AT84CS001 ...
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... W18 DAEN W17 RS L2 SLEEP A18 e2v semiconductors SAS 2009 Function In-phase (+) digital outputs for port the LSB the MSB Inverted phase (-) digital outputs for port B In-phase (+) additional bit output for port B or inverted phase (-) output clock in staggered mode for port B ...
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... VCCD VCCD DRN DRTYPE L VPLUSD VPLUSD RS C0N M DGND DGND C0 C1N N VPLUSD VPLUSD C1 C2N P DGND DGND C2 C3N R VPLUSD VPLUSD C3 C4N T VPLUSD VCCD VCCD VCCD C4 C5N U VPLUSD VPLUSD VPLUSD VCCD C5 C6N COR DRCN CORN W D0N C9N C8N C7N / DRC e2v semiconductors SAS 2009 ...
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... Data and Clock Differential Input Buffer Figure 6-1. LVDS Data and LVDS Clock Input Buffer and Standalone Delay Line Input (DAI, DAIN) in 1.25V ± 0.175V inb 1.25V ± 0.175V e2v semiconductors SAS 2009 VCCD (3.3V ± 5%) ESD: ESD: vccdiode vccdiode C = 435 435 fF 49 ...
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... DGND (0V) VCCD (3.3V ± 5%) 12.7K 399 399 25.0K 9.32K 4.00K 4.00K DGND (0V) AT84CS001 vccdiode vccdiode ESD: ESD: vccdiode vccdiode C = 435 435 fF out outn ESD: ESD: gnddiode gnddiode C = 272 272 fF gnddiode gnddiode SUBST (0V/-5V) 4.00K 4.00K 75 ua e2v semiconductors SAS 2009 ...
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... Standalone Delay Cell Control Input Buffer Figure 6-5. Standalone Delay Cell Control Input Buffer (DACTRL, CLKDACTRL) ESD: vccdiode C = 435 fF in ESD: gnddiode C = 272 fF e2v semiconductors SAS 2009 VCCD (3.3V ± 5%) 4.00K 1.2K ESD: vccdiode C = 435 fF 16.00K ESD: gnddiode C = 272 fF DGND (0V) SUBST (0V/-5V) VCCD (3.3V ± ...
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... AT84CS001 Reduction Reduction Silicon Silicon Junction Junction 0.23 2.95 3.88˚C/watt 1.90 1.60 1.90 1.83 Infinite heatsink at Infinite heatsink at bottom of balls bottom of balls Thermal resistance junction to bottom of balls 5.0˚C/watt max e2v semiconductors SAS 2009 23 °C ± 5 ...
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... These capacitors should be placed as close as possible to the power supply package pins. The minimum required pairs of capacitors by power supply type is: • 15 for V CCD • 14 for V PLUSD Figure 8-2. AT84CS001 Power Supplies Bypassing Scheme e2v semiconductors SAS 2009 1 µF 100 nF Ground AT84CS001 VPLUSD VCCD 100 ...
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... Figure 8-4. AT84CS001 LVDS Output Termination Scheme AT84CS001 32 0809E–BDC–05/09 AT84CS001 50Ω Data or clock in-phase signal 50Ω 50Ω 50Ω Data or clock inverted phase signal 50Ω line 100Ω 50Ω line AT84CS001 Positive output signal Negative output signal e2v semiconductors SAS 2009 ...
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... In the DMUX package above, the die’s underside is attached to the copper heat spreader so the copper heat spreader is at GND (0V). We recommend electrically isolating the copper heat spreader from the heat sink if a heat sink is used, in which case ade- quate low Rth electrical isolation should be used. e2v semiconductors SAS 2009 Copper heat spreader Ni plating (0 ...
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... Ni Plated Top View Detail B A4 Detail A 10. Ordering Information Part Number Package AT84CS001VTP EBGA 240 EBGA 240 AT84CS001VTPY RoHS AT84CS001TP-EB EBGA 240 For lead-free version, please contact your local e2v sales office. 34 0809E–BDC–05/ Detail B D1 Bottom View Detail 0.30 ...
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... Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa- tion contained herein ...