PRIXP421ABB Intel, PRIXP421ABB Datasheet - Page 103

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PRIXP421ABB

Manufacturer Part Number
PRIXP421ABB
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP421ABB

Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PRIXP421ABB
Manufacturer:
ALTERA
Quantity:
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Part Number:
PRIXP421ABB
Manufacturer:
INTEL
Quantity:
20 000
Datasheet—Intel
Figure 31.
Table 58.
June 2007
Document Number:
EX_CLK
EX_CS_N[0]
EX_ADDR[23:0]
EX_ALE
EX_IOWAIT_N
EX_RD_N
(exp_mot_rnw)
EX_WR_N
(exp_mot_ds_n)
EX_DATA[15:0]
Motorola* Multiplexed
Write Mode
Motorola* Multiplexed Write Mode
Motorola* Multiplexed Mode Values (Sheet 1 of 2)
®
Symbol
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
T
252479-007US
T
IXP42X product line and IXC1100 control plane processors
ale2addrhold
T
dval2valds
T
alepulse
dspulse
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
Parameter
Pulse width of EX_ALE (ADDR is valid at the rising edge of
EX_ALE)
Valid address hold time after from falling edge of EX_ALE
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
T
ALE Extended
alepulse
2-5 Cycles
Valid Address
Intel
T1
®
T
T
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
ale2addrhold
ale2valcs
1-4 Cycles
T
T2
dval2valds
Valid Address
1-16 Cycles
Valid Data
T
T3
dspulse
1-4 Cycles
T4
1-16 Cycles
Min.
1
1
1
1
T
T5
recov
Max.
16
4
1
4
Units
Cycles
Cycles
Cycles
Cycles
B3752-001
Datasheet
Notes
1, 2,
1,
3,
4,
7
7
7
103
7

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