SCC2681AC1N28 NXP Semiconductors, SCC2681AC1N28 Datasheet
SCC2681AC1N28
Specifications of SCC2681AC1N28
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SCC2681AC1N28 Summary of contents
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... SCC2681 Dual asynchronous receiver/transmitter (DUART) Product data INTEGRATED CIRCUITS 2004 Apr 06 ...
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... ORDERING INFORMATION Type number Package Name Description Commercial 5 + amb SCC2681AC1A44 PLCC44 plastic leaded chip carrier; 44 leads SCC2681AC1N28 DIP28 plastic dual in-line package; 28 leads (600 mil) SCC2681AC1N40 DIP40 plastic dual in-line package; 40 leads (600 mil) Industrial 10 – + amb SCC2681AE1A44 PLCC44 plastic leaded chip carrier; 44 leads ...
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... DUART and the CPU the least significant bit. I Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When HIGH, places the D0-D7 lines in the 3-State condition. I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the addressed register ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PIN SYMBOL SYMBOL PLCC44 DIP40 DIP28 RxDA RxDB TxDA TxDB OP0 OP1 OP2 31 28 – OP3 15 13 – OP4 30 27 – OP5 16 14 – OP6 29 26 – OP7 17 15 – IP0 8 7 – IP1 5 4 – ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1 ABSOLUTE MAXIMUM RATINGS SYMBOL T Operating ambient temperature range amb T Storage temperature range stg All voltages with respect to ground Pin voltage range NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) AC CHARACTERISTICS – + +5.0 V 10% amb CC SYMBOL SYMBOL Reset Timing (Figure 3) t RESET pulse width RES 6 Bus Timing (Figure 4) t A0-A3 set-up time to RDN, WRN LOW AS t A0-A3 hold time from RDN, WRN LOW AH t CEN set-up time to RDN, WRN LOW ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 9. This parameter is not applicable to the 28-pin device. 10. Operation to 0 MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized. ...
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... Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART external clock is used instead of a crystal, both X1 and X2 should use a configuration similar to the one in Figure 7. ...
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... CR registers. Via appropriate programming they may be just another parallel port to external circuits, or they may represent many internal conditions of the UART. When this 8-bit port is used as a general purpose output port, the output port pins drive a state which is the complement of the Output Port Register (OPR). OPR( results in OP(n) = LOW and vice versa ...
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... A receiver reset will re-align the pointers. Multidrop Mode Note: Please see Application Note AN10251 for more information on this feature. The DUART is equipped with a wake up mode for multidrop applications. This mode is selected by programming bits MR1A[4:3] 2004 Apr 06 or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of operation, a ‘ ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PROGRAMMING The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1. The contents of certain control registers are initialized to zero on RESET ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats BIT 7 BIT 6 RxRTS RxINT CONTROL SELECT MR1A MR1A RxRDY MR1B 1 = Yes 1 = FFULL NOTE block error mode, block error conditions must be cleared by using the error reset command (command 4x receiver reset. ** Please see Receiver Reset note on page 21. ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats (Continued) BIT 7 BIT 6 BRG SET ACR SELECT MODE AND SOURCE 0 = set set 2 BIT 7 BIT 6 DELTA DELTA IPCR Yes 1 = Yes BIT 7 BIT 6 INPUT DELTA PORT ISR BREAK B CHANGE Yes 1 = Yes BIT 7 BIT 6 IN ...
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... MR1A. Accesses to MR2A do not change the pointer. MR2A[7:6] – Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7: the normal mode, with the transmitter and receiver operating independently. MR2A[7: places the channel in the automatic echo mode, which automatically re-transmits the received data ...
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... NOTE: Duty cycle of 16 clock is 50% 1%. Asynchronous UART communications can tolerate frequency error of 4. “clean” communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) CSRA[7:4] – Channel A Receiver Clock Select This field selects the baud rate clock for the Channel A receiver as follows (X1 rate at 3.6864 MHz): CSRA[7:4] ACR[ 0000 50 0001 110 0010 134.5 0011 200 0100 300 0101 600 0110 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) CRB – Channel B Command Register CRB is a register used to supply commands to Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) OPCR – Output Port Configuration Register OPCR[7] – OP7 Output Select This bit programs the OP7 output to provide one of the following: 0 – The complement of OPR[7]. 1 – The Channel B transmitter interrupt output which is the complement of TxRDYB. When in this mode OP7 acts as an Open-drain output ...
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... ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 00 when the DUART is reset. 16 ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0] ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) masked off through the OPCR[3: until the T/C is programmed to the desired operational state. In the counter mode, the C/T counts down the number of pulses loaded into CTUR and CTLR by the CPU. Counting begins upon receipt of a counter command. Upon reaching terminal count (0x0000), the counter ready interrupt bit (ISR[3]) is set ...
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... NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68692 and SCC2698B” ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TIMING DIAGRAMS RESET A0– CEN t CS RDN D0–D7 FLOAT (READ) WDN D0–D7 (WRITE) RDN IP0–IP6 WRN OP0–OP7 2004 Apr 06 t RES Figure 3. Reset Timing RWD NOT VALID FLOAT VALID t RWD VALID Figure 4. Bus Timing ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TIMING DIAGRAMS (Continued) NOTES: 1. INTRN or OP3 – OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from themidpoint of the switching signal, V point 0.5V above V ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TxC (INPUT) TxD TxC (1X OUTPUT) TIMING DIAGRAMS (Continued) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) WRN CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 2004 Apr 06 1 BIT TIME ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TIMING DIAGRAMS (Continued) D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP5) RDN STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR( and MR( MASTER STATION ADD#1 TxD TRANSMITTER ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP28: plastic dual in-line package; 28 leads (600 mil) 2004 Apr 06 26 Product data SCC2681 SOT117-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 2004 Apr 06 27 Product data SCC2681 SOT129-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2004 Apr 06 28 Product data SCC2681 SOT187-2 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) REVISION HISTORY Rev Date Description _1 20040406 Product data (9397 750 12075). ECN 853-2445 01-A15014 of 15 December 2003. Data sheet status Product [1] Level Data sheet status [2] [3] status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design ...