MT8815AP1 Zarlink, MT8815AP1 Datasheet
MT8815AP1
Specifications of MT8815AP1
Related parts for MT8815AP1
MT8815AP1 Summary of contents
Page 1
... Decoder AY0 AY1 AY2 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2008, Zarlink Semiconductor Inc. All Rights Reserved. MT8815AP1 MT8815APR MT8815APR1 44 Pin PLCC* MT8815AE1 Description The Zarlink MT8815 is fabricated in Zarlink’s ISO- CMOS technology providing low power dissipation and high reliability ...
Page 2
... X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 15, Connection Analog (Input/Output): this is connected to the Y7 column of the switch array Digital Ground Reference (Input). SS MT8815 Change MT8815AE removed - obsolete. Added pb free part numbers X10 13 14 X11 PIN PLCC Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet ...
Page 3
... Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High Analog (Input/Output): this is connected to the Y2 column of the switch array Connection. MT8815 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
Page 4
... DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. MT8815 and V ) are provided for the MT8815 to enable switching of negative while the range for analog signals is from Zarlink Semiconductor Inc. Data Sheet “0” turning off all crosspoint to DD ...
Page 5
... ‡ Sym. Min. Typ. Max 100 DD 0.4 1 ±1 ±500 I OFF V 0.8 2.0 3 0.1 10 LEAK 5 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 15.0 V -0 -0 -0 ±15 mA °C -65 +150 0.6 W Units Test Conditions ° ...
Page 6
... V ‡ Sym. Min. Typ. Max 0 3dB THD 0.01 FDT -95 X -45 talk -90 -85 - Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Ω =0V Ω 0. Ω See Appendix, Fig. A.2 Ω V =12V = / 0. See Appendix, Fig ...
Page 7
... RPW t 40 100 100 100 R See Fig. 3 for control and I/O timing details. 50 Figure 3 - Control Memory Timing Diagram 7 Zarlink Semiconductor Inc. Data Sheet =5V, V =0V Units Test Conditions mVpp V =3V squarewave =1kΩ, R =10kΩ See Appendix, Fig. A.6 pF f=1MHz MHz 1kΩ, ...
Page 8
... Zarlink Semiconductor Inc. Data Sheet AY2 Connection 0 X0-Y0 0 X1-Y0 0 X2-Y0 0 X3-Y0 0 X4-Y0 0 X5- Connection 0 No Connection 0 X6-Y0 0 X7-Y0 0 X8-Y0 0 X9-Y0 0 X10-Y0 0 X11- Connection 0 No Connection 0 X0-Y1 ↓ ↓ ↓ ...
Page 9
...
Page 10
...
Page 11
... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...