5962-8512702XA Analog Devices Inc, 5962-8512702XA Datasheet
5962-8512702XA
Specifications of 5962-8512702XA
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5962-8512702XA Summary of contents
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AD574A–SPECIFICATIONS Model RESOLUTION LINEARITY ERROR @ + MIN MAX DIFFERENTIAL LINEARITY ERROR (Minimum Resolution for Which No Missing Codes are Guaranteed MIN MAX UNIPOLAR OFFSET (Adjustable to Zero) BIPOLAR OFFSET (Adjustable to Zero) ...
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Model RESOLUTION LINEARITY ERROR @ + MIN MAX DIFFERENTIAL LINEARITY ERROR (Minimum Resolution for Which No Missing Codes are Guaranteed MIN MAX UNIPOLAR OFFSET (Adjustable to Zero) BIPOLAR OFFSET (Adjustable to Zero) FULL-SCALE ...
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AD574A +5V SUPPLY DATA MODE SELECT CHIP SELECT BYTE ADDRESS/ SHORT CYCLE READ/CONVERT CHIP ENABLE +12/+15V SUPPLY +10V REFERENCE ANALOG COMMON REFERENCE INPUT -12/-15V SUPPLY BIPOLAR OFFSET 10V SPAN INPUT 20V SPAN INPUT ABSOLUTE MAXIMUM RATINGS* (Specifications apply to all ...
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THE AD574A OFFERS GUARANTEED MAXIMUM LINEARITY ERROR OVER THE FULL OPERATING TEMPERATURE RANGE DEFINITIONS OF SPECIFICATIONS LINEARITY ERROR Linearity error refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used ...
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AD574A CIRCUIT OPERATION The AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete successive- approximation analog-to-digital conversion function. A block diagram of the AD574A is shown in Figure 1. +5V SUPPLY 1 V ...
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–V REF S AGND 100 10k 10k GAIN +15V 100pF R4 100k R1 100k A1 OFFSET AD585 R3 –15V 100 ...
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AD574A The full-scale trim is done by applying a signal 1 1/2 LSB below the nominal full scale (9.9963 for range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111). BIPOLAR OPERATION ...
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Figure 7 shows a complete timing diagram for the AD574A con- vert start operation. R/C should be low before both CE and CS are asserted; if R/C is high, a read operation will momentarily occur, possibly resulting in system bus ...
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AD574A to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid. If conversion is initiated by a high pulse as ...
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Figure 15. Z80—AD574A Interface Figure 16. Wait State Generator IBM PC Interface The AD574A appears in Figure 17 interfaced to the 4 MHz 8088 processor of an IBM PC. Since the device resides in I/O space, its address is decoded ...
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AD574A 28-Pin Ceramic DIP Package (D-28) 0.048 (1.21) 0.042 (1.07) 0.458 (11.63) 0.442 (11.23) 0.075 (1.91) REF 0.075 (1.91) REF OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Terminal PLCC Package (P-28A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.056 (1.42) ...