874001AGI-05LF Integrated Device Technology (Idt), 874001AGI-05LF Datasheet - Page 2

• Manufacturer Part Number: 874001AGI-05LF
• Description: PCI Express Jitter Attenuator 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 874001AGI-05LF

• Package: 20TSSOP
• Operating Temperature: -40 to 85 °C

ICS74001I-05 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS874001AGI-05 REVISION A JANUARY 14, 2011
Symbol
C
R
R
IN
PULLUP
PULLDOWN
15, 16, 20
2, 3, 4, 6,
Number
17, 18
10
11
12
13
14
19
1
5
7
8
9
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
PLL_SEL
F_SEL1
F_SEL0
Name
nQ, Q
nCLK
V
V
GND
CLK
V
MR
OE
nc
DDO
DDA
DD
Unused
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Test Conditions
Description
PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL.
LVCMOS/LVTTL interface levels. See Table 3B.
No connect.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go LOW and the inverted output nQ to go HIGH.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Analog supply pin.
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
Output enable. When HIGH, outputs are enabled. When LOW, forces outputs
to a High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Output supply pin.
2
Minimum
©2011 Integrated Device Technology, Inc.
Typical
PCI EXPRESS™ JITTER ATTENUATOR
51
51
4
Maximum
Units
k
k
pF
Ω
Ω