74AHCT125D NXP Semiconductors, 74AHCT125D Datasheet

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74AHCT125D

Manufacturer Part Number
74AHCT125D
Description
Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin SO Tube
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AHCT125D

Package
14SO
Logic Family
AHCT
Logic Function
Buffer/Line Driver
Number Of Outputs Per Chip
4
Output Type
3-State
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
7.5@4.5V to 5.5V ns
Polarity
Non-Inverting

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74AHCT125D
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74AHCT125D
Manufacturer:
NXP
Quantity:
10 954
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC125D
74AHCT125D
74AHC125PW
74AHCT125PW
74AHC125BQ
74AHCT125BQ
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active
LOW enable inputs.
74AHC125; 74AHCT125
Quad buffer/line driver; 3-state
Rev. 04 — 11 January 2008
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
For 74AHC125 only: operates with CMOS input levels
For 74AHCT125 only: operates with TTL input levels
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
SO14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5
3
CC
0.85 mm
Product data sheet
Version
SOT108-1
SOT402-1
SOT762-1

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74AHCT125D Summary of contents

Page 1

... CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from +85 C and from +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC125D +125 C 74AHCT125D 74AHC125PW +125 C 74AHCT125PW 74AHC125BQ +125 C 74AHCT125BQ CC Description SO14 plastic small outline package; 14 leads; ...

Page 2

... NXP Semiconductors 4. Functional diagram 1OE 2OE 3OE 4OE 13 mna228 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74AHC125 74AHCT125 1OE 2OE GND 7 001aae755 Fig 4. Pin configuration SO14 and TSSOP14 74AHC_AHCT125_4 Product data sheet 74AHC125; 74AHCT125 EN1 mna229 Fig 2. IEC logic symbol ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW data input 1Y 3 data output 2OE 4 output enable input (active LOW data input 2Y 6 data output GND 7 ground ( data output 3A 9 data input 3OE ...

Page 4

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter T storage temperature stg P total power dissipation tot SO14 package TSSOP14 package DHVQFN14 package [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

Page 5

... NXP Semiconductors Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA OFF-state output current GND 5 input leakage GND current 5 supply current GND 5 input I capacitance C output O capacitance ...

Page 6

... NXP Semiconductors Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I additional per input pin; CC supply current other pins 4 5 input I capacitance C output O capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74AHCT125 t propagation nA to nY; see pd delay enable time nOE to nY; see 4 5 disable time nOE to nY; see dis power pF dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V ...

Page 8

... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Enable and disable times Table 8. Measurement points Type Input V M 74AHC125 0.5V CC 74AHCT125 1 ...

Page 9

... NXP Semiconductors negative positive PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Load circuit for switching times Table 9. Test data ...

Page 10

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A (1) UNIT max. 0.05 0.30 3 0.2 0.00 0.18 2.9 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Document ID Release date 74AHC_AHCT125_4 20080111 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...

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