MT46V64M8P-5B:F Micron Technology Inc, MT46V64M8P-5B:F Datasheet
MT46V64M8P-5B:F
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MT46V64M8P-5B:F Summary of contents
Page 1
... Notes: 1. End of life 2 167 200 167 n/a 167 n/a 133 n/a 133 n/a 1 512Mb: x4, x8, x16 DDR SDRAM Data-Out Access Window Window 1.6ns ±0.70ns 2.1ns ±0.70ns 2.0ns ±0.70ns 2.5ns ±0.75ns 2.5ns ±0.75ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 2
... FBGA (Pb-free 5ns - 6ns 2 6ns 2.5 - 7.5ns -75E 7.5ns -75Z 7.5ns 2.5 -75 2 512Mb: x4, x8, x16 DDR SDRAM 64 Meg Meg Meg banks 8K 8K (A0–A12) 8K (A0–A12) 4 (BA0, BA1) 4 (BA0, BA1) 2K (A0-A9, A11) 1K (A0–A9) Yes Yes Yes Yes Yes ...
Page 3
... SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Power-down (CKE Not Active .90 PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDRTOC.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2000 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 512Mb: x4, x8, x16 DDR SDRAM State Diagram Self refresh REFS REFSX Idle REFA ...
Page 5
... READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access ...
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... Ambient and case temperatures cannot be less than –40°C or greater than +105°C PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM Functional Description Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Functional Block Diagrams The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a 4-bank DRAM. Figure 3: 128 Meg x 4 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTERS COUNTER 15 13 A0–A12, ADDRESS ...
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... DECODER SENSE AMPLIFIERS I/O GATING 2 DM MASK LOGIC BANK CONTROL LOGIC 2 DECODER COLUMN- 9 ADDRESS 10 COUNTER/ LATCH 1 8 512Mb: x4, x8, x16 DDR SDRAM Functional Block Diagrams BANK3 BANK2 DATA READ MUX LATCH 8 DQS GENERATOR COL0 INPUT 16 REGISTERS 1 1 MASK ...
Page 9
... NC LDM 20 WE# WE# 21 CAS# CAS# 22 RAS# RAS# 23 CS# CS BA0 BA0 26 BA1 BA1 27 A10/AP A10/ Micron Technology, Inc., reserves the right to change products or specifications without notice. 9 512Mb: x4, x8, x16 DDR SDRAM x16 DQ7 NF 65 DQ15 DQ14 DQ13 DQ6 DQ3 DQ12 DQ5 ...
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... UDM LDM CK# WE# CAS# G A12 CS# CKE RAS# H A11 A9 BA1 BA0 A10 512Mb: x4, x8, x16 DDR SDRAM DNU DNU DQ1 Q DQ3 DQ5 Q DQ7 DNU Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
Page 11
... Data input/output: Data bus for x16. I/O Data input/output: Data bus for x8. I/O Data input/output: Data bus for x4. Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 512Mb: x4, x8, x16 DDR SDRAM LOW level HIGH, after which it ©2000 Micron Technology, Inc. All rights reserved. ...
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... Do not use: Must float to minimize noise on V Type Description Input Address input A13 for 1Gb devices. Micron Technology, Inc., reserves the right to change products or specifications without notice. 12 512Mb: x4, x8, x16 DDR SDRAM . REF ©2000 Micron Technology, Inc. All rights reserved. ...
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... Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. Not all packages will have the half moon shaped notches as shown. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM SEE DETAIL A 0.71 0.10 (2X) 11.76 ±0.20 10.16 ± ...
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... CTR 1.00 TYP 6.25 ±0. 12.50 ±0. 5.00 ±0.05 14 512Mb: x4, x8, x16 DDR SDRAM Package Dimensions SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: Ø .33 NON SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL # ...
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... Continuous burst 0mA OUT RFC = RFC (MIN RFC = 7.8µ RFC = 1.95µs (AT Standard DD I Low power ( (MIN); Address and 15 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6, -6T, -75E, -75Z, -75 155 130 130 115 1 185 160 160 145 ...
Page 16
... CK (MIN 0mA OUT RFC = RFC (MIN RFC = 7.8µ RFC = 1.95µs (AT Standard DD I Low power ( (MIN); Address and 16 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6, -6T, -75E, -75Z, -75 155 130 130 115 1 195 160 160 145 ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – RFC REFI 9 n/a n/a 8 n/a n/a 10 n/a n/a 11 n/a n/a 9 n/a n/a 9 n/a n/a 8 n/a ...
Page 18
... I OUT OL , REF ) OHR OUT ) OLR OUT , REF ) 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Min Max –1V +3.6V –1V +3.6V –1V +3.6V –0. 0.5V DD –55 +150 – +2.6V ±0.1V Min Max Units +2.5 +2.7 +2.5 +2.7 0.49 × 0.51 × V ...
Page 19
... I OLR OUT , REF ) +2.5V ±0.2V +2.5V ±0. Symbol REF AC 19 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and +2.5V ±0.2V Min Max Units +2.3 +2.7 +2.3 +2.7 0.49 × 0.51 × 0. 0.04 REF REF 0.3 REF DD –0 0.15 REF – ...
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... V TT 25Ω Reference 25Ω point Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Receiver ©2000 Micron Technology, Inc. All rights reserved ...
Page 21
... DD Symbol 0.5 × MIN when static and is centered around 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and +2.6V ±0.1V +2.6V ±0.1V for -5B Min Max Units 1.15 1.35 –0 0 0 0.2 0.5 × 0 Maximum clock level ...
Page 22
... Delta input capacitance: CK, CK# Input/output capacitance: DQ, LDQS, UDQS, LDM, UDM Input capacitance: Command and address Input capacitance: CK, CK# Input capacitance: CKE PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Symbol Min DC – – ...
Page 23
... QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI t RFC RPRE t RPST t RRD t VTD t WPRE t WPRES t WPST 23 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units –0.70 +0. 0. 0.45 0.55 CK 0.40 – ns 1.75 – ns –0.60 +0. 0.35 – ...
Page 24
... Data valid output window PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev +2.6V ±0.1V +2.6V ±0.1V DD Symbol WTR t XSNR t XSRD n/a 24 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units 15 – – – 200 – ...
Page 25
... QH t QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI t RFC RPRE t RPST t RRD t VTD t WPRE 25 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6 (FBGA) Min Max Units –0.70 +0. 0. 0.45 0.55 CK 0.45 – ns 1.75 – ns –0.6 +0 0.35 – ...
Page 26
... Data valid output window PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev +2.5V ±0.2V +2.5V ±0.2V DD Symbol t WPRES t WPST WTR t XSNR t XSRD n/a 26 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6 (FBGA) Min Max Units 0 – 0.4 0 – – – ...
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... QH t QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI t RFC RPRE t RPST t RRD t VTD t WPRE 27 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units –0.70 +0. 0. 0.45 0.55 CK 0.45 – ns 1.75 – ns –0.6 +0 0.35 – ...
Page 28
... Data valid output window PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev +2.5V ±0.2V +2.5V ±0.2V DD Symbol t WPRES t WPST WTR t XSNR t XSRD n/a 28 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units 0 – 0.4 0 – – – ...
Page 29
... QH t QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI t RFC RPRE t RPST t RRD t VTD t WPRE 29 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75E Min Max Units –0.75 +0. 0.45 0. 0.45 0.55 CK 0.5 – ns 1.75 – ns –0.75 +0. 0.35 – ...
Page 30
... Data valid output window PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev +2.5V ±0.2V +2.5V ±0.2V DD Symbol t WPRES t WPST WTR t XSNR t XSRD n/a 30 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75E Min Max Units 0 – 0.4 0 – – – ...
Page 31
... QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI t RFC RPRE t RPST t RRD t VTD t WPRE t WPRES 31 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75Z Min Max Units –0.75 +0. 0.45 0. 0.45 0.55 CK 0.5 – ns 1.75 – ns –0.75 +0. 0.35 – ...
Page 32
... Data valid output window PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev +2.5V ±0.2V +2.5V ±0.2V DD Symbol t WPST WTR t XSNR t XSRD n/a 32 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75Z Min Max Units t 0.4 0 – – – ...
Page 33
... QH t QHS t RAP t RAS RCD t REFC t REFC t REFI t REFI RPRE t RPST t RRD t VTD t WPRE t WPRES 33 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Min Max Units –0.75 +0. 0.45 0. 0.45 0.55 CK 0.5 – ns 1.75 – ns –0.75 +0. 0.35 – ...
Page 34
... Symbol tWPST tWR t WTR t XSNR t XSRD n +2.5V ±0.2V +2.5V ±0. 1.00 1.05 1. +2.5V ±0.2V +2.5V ±0. 0.50 0.55 0.60 34 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Min Max Units 0.4 0.6 tCK 15 – – – 200 – DQSQ ...
Page 35
... Specified values are obtained specifications are tested after the device is properly initialized and is averaged at = +2.5V ±0.2V 25° OUT 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -to-V swing 1.5V in the test environ- IH (or to the crossing point for CK/CK#), REF ( ) and ...
Page 36
... However, an AUTO REFRESH command must be asserted at least once every 70.3µs(commerial and industrial) or 17.55µs (automotive); burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device ...
Page 37
... V-I curve of Figure 13 on page 38. limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 13 on page 38. 37 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC - 7.5ns -75E / - 7.5ns - 6ns ...
Page 38
... V-I curve of Figure 15 on page 39. and voltage will lie within the outer bounding lines of the V-I curve of Figure 16. 38 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2 ...
Page 39
... V Q must track each other DQSCK (MAX DQSCK (MIN) + RPRE (MAX) condition. 39 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2.0 2.5 level and the referenced test DD pulse width ≤ 3ns, and the pulse t RPST (MAX) condition. ...
Page 40
... Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ± ...
Page 41
... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Nominal Min Max Low 4.6 9.6 –6.1 9.2 18.2 –12.2 13.8 26.0 – ...
Page 42
... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Nominal Min Max Low 2.6 5.0 –3.5 5.2 9.9 –6.9 7.8 14.6 – ...
Page 43
... Table 29: Truth Table 2 – DM Operation Used to mask write data, provided coincident with the corresponding data Name (Function) Write enable Write inhibit PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM CS# RAS# CAS# WE ...
Page 44
... RCD is met, the bank will be in the “row active” state. auto precharge enabled and ends when will be in the idle state. auto precharge enabled and ends when will be in the idle state. 44 512Mb: x4, x8, x16 DDR SDRAM is HIGH (see Table 33 on page 47) and has been met. t RCD has been met ...
Page 45
... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev met. Once RFC is met, the DDR SDRAM will be in the all banks idle state MRD has been met. Once MRD is met, the DDR SDRAM will be in the all banks idle state ...
Page 46
... The minimum delay from a READ or WRITE command with auto precharge enabled command to a different bank is summarized in Table 32. To Command PRECHARGE ACTIVE PRECHARGE ACTIVE 46 512Mb: x4, x8, x16 DDR SDRAM t RP has been met. t RCD has been met. No data t WR ends, with t RP) begins. This device supports ...
Page 47
... H Notes: 1. CKE clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay ...
Page 48
... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN HIGH Row Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 512Mb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 49
... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 512Mb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 50
... Ai is the most significant column address bit for a given density ( HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 512Mb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 51
... All banks must be idle before an AUTO REFRESH command is issued. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). ...
Page 52
... DLL bit (set LMR command is issued, the same operating parameters should be utilized as in step 11. 20. Wait at least 21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with CKE HIGH are required between step 11 (DLL RESET) and any READ command. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N ...
Page 53
... Issue AUTO REFRESH command Assert NOP or DESELECT for t RFC time Optional LMR command to clear DLL bit Assert NOP or DESELECT for t MRD time DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 512Mb: x4, x8, x16 DDR SDRAM Operations © ...
Page 54
... V , and V + 0.3V. Alternatively, V REF are 0V, provided a minimum of 42Ω of series resistance is used between DD DD supply and the input pin. Once initialized 512Mb: x4, x8, x16 DDR SDRAM Tc0 Td0 Te0 ( ( ( ( ( ( ) ) ) ) ...
Page 55
... REGISTER DEFINITION Mode Register The mode register is used to define the specific DDR SDRAM mode of operation. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 23. The mode register is programmed via the LMR command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or until the device loses power (except for bit A8, which is self- clearing) ...
Page 56
... Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 23 on page 55. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command locations are available for both the sequential and the interleaved burst types ...
Page 57
... NOP READ NOP NOP READ NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 512Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n NOP T2n T3 T3n NOP T3 T3n NOP Don’t Care AC, DQSCK, and DQSQ. ...
Page 58
... DDR SDRAM 133 ≤ f ≤ 200 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
Page 59
... RCD specification. t RCD specification of 20ns with a 133 MHz clock (7.5ns period ≤ 3 (Figure 26 also shows the same case for RCD (MIN)/ 59 512Mb: x4, x8, x16 DDR SDRAM Address bus Extended mode DS DLL register (Ex) DLL E0 0 Enable ...
Page 60
... CK and CK#). Figure 27 on page 62 shows the general timing for each possible CL setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble ...
Page 61
... RP have been met. Part of the row precharge time is hidden during the access of the last data elements. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM t DQSS (NOM) case is shown; the t DQSS [MIN] and Micron Technology, Inc ...
Page 62
... NOP NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 62 512Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 NOP NOP T3n T4 T5 NOP NOP T3n T4 T4n T5 NOP NOP Transitioning Data Don’t Care ...
Page 63
... Bank, Col 2 NOP READ NOP Bank, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 63 512Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T4n T5 T5n NOP NOP DO b T3n T4 T4n T5 T5n NOP NOP DO b T3n T4 T4n T5 ...
Page 64
... Bank, Col 2 NOP NOP READ Bank, Col AC, DQSCK, and Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 512Mb: x4, x8, x16 DDR SDRAM T3n T4 T5 T5n NOP NOP DO b T3n T4 T5 T5n NOP NOP DO T3n T4 T4n T5 NOP NOP Transitioning Data Don’ ...
Page 65
... Col x Col b Col 2 READ READ READ Bank, Bank, Bank, Col x Col b Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 65 512Mb: x4, x8, x16 DDR SDRAM Operations T4 T4n T5 T5n NOP NOP T3n T4 T4n T5 T5n NOP NOP ...
Page 66
... BST 1 NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 512Mb: x4, x8, x16 DDR SDRAM Operations T4 T5 NOP NOP T4 T5 NOP NOP T3n T4 T5 NOP NOP Transitioning Data Don’t Care ©2000 Micron Technology, Inc. All rights reserved. ...
Page 67
... NOP BST BST NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 67 512Mb: x4, x8, x16 DDR SDRAM Operations T4 T4n T5 T5n NOP NOP DI b T3n T4 T5 T5n WRITE NOP Bank, Col b t DQSS (NOM ...
Page 68
... RAS (MIN) is met, a READ command with auto precharge enabled would cause AC, DQSCK, and DQSQ. t RAS (MIN) is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 512Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 NOP ACT Bank a, Row t RP T3n ...
Page 69
... NOP READ NOP Col Bank RCD t RAS RPRE t LZ (MIN (MIN) Micron Technology, Inc., reserves the right to change products or specifications without notice. 69 512Mb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n PRE NOP NOP All banks One bank 5 Bank DQSCK (MIN) RPST (MIN) ...
Page 70
... DQS DQ (last data valid (last data valid) 6 Earliest signal transition Latest signal transition clock transition collectively when a bank is active HP QHS. 70 512Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 T3n DQSQ 2 t DQSQ T2n T3 T2 T2n T3 T2 T2n T3 Data Data Data valid valid valid ...
Page 71
... Data valid window window t DQSQ 2 t DQSQ Data valid window clock transition collectively when a bank is active HP QHS. 71 512Mb: x4, x8, x16 DDR SDRAM T3 T3n DQSQ 2 t DQSQ T2n T3 T3n T2n T3 T3n T2n T3 T3n Data valid Data valid window window t DQSQ 2 t DQSQ 2 ...
Page 72
... DQSQ after DQS transitions, regardless (MIN) are the first valid signal transitions (MAX) are the latest valid signal transitions DQSS [MIN] and DQSS [MAX]) might not be intuitive; they have also been 72 512Mb: x4, x8, x16 DDR SDRAM T3 T3n T4 T4n T5 t DQSCK 2 (MAX) t DQSCK 2 (MIN) T3 T3n ...
Page 73
... DM, as shown in Figures 46 and 47. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 512Mb: x4, x8, x16 DDR SDRAM t WTR should be met, as shown in Figure period are written to the internal array; any subsequent data-in Micron Technology, Inc ...
Page 74
... Bank a, Col b t DQSS DQS DQSS DQS DQSS DQS Transitioning Data 74 512Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 NOP NOP Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations ...
Page 75
... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n NOP WRITE Bank, Col n t DQSS 512Mb: x4, x8, x16 DDR SDRAM T3 T3n T4 T4n T5 NOP NOP NOP DI n Transitioning Data Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 76
... Bank, Col b t DQSS DQS T1n WRITE WRITE WRITE Bank, Bank, Bank, Col b Col x t DQSS (NOM 512Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 T4 NOP WRITE NOP Bank, Col Transitioning Data T2 T2n T3 T3n T4 T4n WRITE WRITE Bank, Bank, Col n Col a Col g ...
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... T1n T2 T2n T3 NOP NOP NOP t WTR 512Mb: x4, x8, x16 DDR SDRAM T4 T5 READ NOP Bank a, Col Transitioning Data t WTR is not required, and the READ Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
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... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col 512Mb: x4, x8, x16 DDR SDRAM T3n T4 T5 T5n NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col 512Mb: x4, x8, x16 DDR SDRAM T5n T3n T4 T5 NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n T3 NOP NOP NOP 512Mb: x4, x8, x16 DDR SDRAM T4 T5 PRE NOP Bank all) Transitioning Data not required, and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
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... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n T3 NOP NOP NOP 512Mb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 NOP PRE t RP Bank all) Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’ ...
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... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev T1n T2 T2n T3 NOP NOP NOP 512Mb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 PRE NOP t RP Bank all) Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’ ...
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... Bank x t RCD t RAS t DQSS (NOM WPRES WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 83 512Mb: x4, x8, x16 DDR SDRAM T4n T5 T5n T6 T7 NOP 1 NOP 1 NOP DQSL DQSH WPST Transitioning Data ©2000 Micron Technology, Inc. All rights reserved. ...
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... NOP WRITE NOP Col Bank x t RCD t RAS t DQSS (NOM) t WPRES t WPRE 512Mb: x4, x8, x16 DDR SDRAM T4n T5 T5n NOP NOP NOP DQSL t DQSH t WPST Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
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... DQSH Transitioning Data t DQSS (MIN). t DQSS (MAX). Micron Technology, Inc., reserves the right to change products or specifications without notice. 85 512Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 t DSS 3 t WPST Don’t Care t RP) after the t RAS (MIN), as described for t RP) is completed. ...
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... READ NOP Col Bank x t RCD, t RAP RAS RPRE t LZ (MIN (MIN) t RAS has been satisfied. Micron Technology, Inc., reserves the right to change products or specifications without notice. 86 512Mb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n NOP NOP NOP DQSCK (MIN) t RPST (MIN) ...
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... AUTO REFRESH command and the next AUTO REFRESH command is 9 × specifications exceed the JEDEC requirement by one clock. This maximum absolute interval is to allow future support for DLL updates, internal to the DDR SDRAM restricted to AUTO REFRESH cycles, without allowing excessive drift in updates. ...
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... DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown. SELF REFRESH When in the self refresh mode, the DDR SDRAM retains data without external clocking. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “ ...
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... XSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command can be applied general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the ...
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... Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined when the read postamble is satisfied; for WRITEs, when the write recovery time ...
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... DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev Valid 2 NOP Valid Enter 3 power-down mode must always be powered within the specified range. REF Micron Technology, Inc., reserves the right to change products or specifications without notice. 91 512Mb: x4, x8, x16 DDR SDRAM Ta0 Ta1 ( ( ) ) ( ( ) ) NOP ( ( ) ) ( ( ) ) ( ( ) ) ( ...