MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet

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MT48LC2M32B2TG-6:G

Manufacturer Part Number
MT48LC2M32B2TG-6:G
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC2M32B2TG-6:G

Density
64 Mb
Maximum Clock Rate
166 MHz
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
0 to 70 °C
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC2M32B2TG-6:G
Quantity:
27
Part Number:
MT48LC2M32B2TG-6:G
Manufacturer:
MT
Quantity:
20 000
Synchronous DRAM
MT48LC2M32B2 – 512K x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode (not available on AT devices)
• Refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. J 12/08 EN
Options
• Configuration
• Plastic package – OCPL
• Timing (cycle time)
• Die revision
• Operating temperature range
edge of system clock
changed every clock cycle
and auto refresh modes
– 64ms, 4,096-cycle refresh (15.6µs/row)
– 16ms, 4,096-cycle refresh (3.9µs/row)
– 2 Meg x 32 (512K x 32 x 4 banks)
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm) Pb-free
– 5ns (200 MHz)
– 5.5ns (183 MHz)
– 6ns (166 MHz)
– 7ns (143 MHz)
– Commercial (0° to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
(commercial, industrial)
(automotive)
2. Available on -6 and -7.
3. Contact Micron for product availability.
Products and specifications discussed herein are subject to change by Micron without notice.
1
Marking
2M32B2
None
AT
-55
IT
TG
B5
:G
-5
-6
-7
P
2
3
1
Table 1:
Table 2:
Table 3:
Notes: 1. FBGA Device Decode: http://
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
MT48LC2M32B2TG
MT48LC2M32B2P
MT48LC2M32B2B5
Speed
Grade
-55
-5
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Part Number
www.micron.com/support/FBGA/FBGA.asp
Frequency
200 MHz
183 MHz
166 MHz
143 MHz
Address Table
Key Timing Parameters
CL = CAS (READ) latency
64Mb (x32) SDRAM Part Number
Clock
MT48LC2M32B2P-7:G
Part Number Example:
1
Access
CL = 3
Time
4.5ns
5.5ns
5.5ns
5ns
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
512K x 32 x 4 banks
Architecture
4 (BA0, BA1)
2K (A0–A10)
2 Meg x 32
256 (A0–A7)
Setup
2 Meg x 32
2 Meg x 32
2 Meg x 32
Time
1.5ns
1.5ns
1.5ns
2ns
4K
Features
Hold
Time
1ns
1ns
1ns
1ns

Related parts for MT48LC2M32B2TG-6:G

MT48LC2M32B2TG-6:G Summary of contents

Page 1

... Speed Clock Grade Frequency -5 200 MHz -55 183 MHz -6 166 MHz -7 143 MHz Marking Table 3: 64Mb (x32) SDRAM Part Number 2M32B2 Part Number TG MT48LC2M32B2TG P MT48LC2M32B2P B5 MT48LC2M32B2B5 -5 Notes: 1. FBGA Device Decode: http:// -55 www.micron.com/support/FBGA/FBGA.asp - MT48LC2M32B2P-7:G None Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 2

... A0–A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...

Page 3

... Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Electrical Specifications .43 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Timing Diagrams .51 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32TOC.fm - Rev. J 12/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2001 Micron Technology, Inc. All rights reserved. 64Mb: x32 SDRAM Table of Contents ...

Page 4

... Figure 48: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Figure 49: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 50: 86-Pin Plastic TSOP II (400 mil .68 Figure 51: 90-Ball VFBGA (8mm x 13mm .69 PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32LOF.fm - Rev. J 12/ RCD (MIN) when 2 < RCD (MIN)/ 4 64Mb: x32 SDRAM List of Figures .20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 5

... List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 3: 64Mb (x32) SDRAM Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 4: Pin/Ball Descriptions Table 5: Burst Definition .14 Table 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 7: Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 9: Truth Table 3 – Current State Bank n, Command to Bank .39 Table 10: Truth Table 4 – ...

Page 6

... CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 11 11 A0–A10, ADDRESS 13 BA0, BA1 REGISTER PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN BANK 0 11 BANK 0 ROW- 11 ROW- ADDRESS ADDRESS MUX MEMORY 2048 LATCH & (2,048 x 256 x 32) DECODER SENSE AMPLIFIERS I/O GATING ...

Page 7

... CAS# RAS# CS# NC BA0 BA1 A10 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 V DD Note: The # symbol indicates signal is active LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Pin/Ball Assignments and Descriptions DQ15 DQ14 5 82 DQ13 DQ12 8 79 DQ11 DQ10 ...

Page 8

... Figure 3: 90-Ball VFBGA (Top View, Ball Down PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Pin/Ball Assignments and Descriptions DQ26 DQ24 V SS DQ28 DQ27 DQ25 DQ29 DQ30 DQ31 DQM3 CLK CKE A9 DQM1 DQ8 DQ10 DQ9 DQ12 DQ14 SS DQ11 DQ13 DQ15 64Mb: x32 SDRAM ...

Page 9

... Pin/Ball Assignments and Descriptions Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...

Page 10

... K2, K3, H9 Functional Description In general, this 64Mb SDRAM (512K banks 4-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. ...

Page 11

... Issue an AUTO REFRESH command. 11. Wait at least are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register ...

Page 12

... Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CL, an operating mode and a write burst mode, as shown in Figure 4 on page 13. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored infor- mation until it is programmed again or the device loses power. Mode register bits M0– ...

Page 13

... Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 5 on page 14. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ ...

Page 14

... T2, as shown in Figure 5 on page 15. Table 6 on page 15 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Starting Column Address ...

Page 15

... Figure 5: CAS Latency COMMAND COMMAND COMMAND Table 6: CAS Latency Speed -5 - PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP OUT CLK READ NOP CLK READ NOP Allowable Operating Frequency (MHz – – ≤ 50 ≤ 100 ≤ 50 ≤ 100 15 64Mb: x32 SDRAM ...

Page 16

... A0–A10 define the op-code written to the mode register. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23; and DQM3 controls DQ24–DQ31. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN CS# RAS# CAS# WE# DQM ...

Page 17

... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform an NOP to an SDRAM that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...

Page 18

... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2 ...

Page 19

... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 6 on page 20. ...

Page 20

... CAS latency after the READ command. Each subsequent data- out element will be valid by the next positive clock edge. Figure 9 on page 22 shows general timing for each possible CAS latency setting. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN HIGH ROW ADDRESS ...

Page 21

... This is shown in Figure 10 on page 23 for and data element either the last of a burst of four or the last desired of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...

Page 22

... Figure 9: CAS Latency COMMAND COMMAND COMMAND PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP OUT CLK READ NOP CLK READ NOP 64Mb: x32 SDRAM NOP OUT NOP NOP OUT t AC DON’T CARE UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 23

... Figure 10: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK, COL OUT OUT CLK READ NOP NOP BANK, COL n D OUT ...

Page 24

... WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided given system PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK ...

Page 25

... Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 12 and in Figure 13 on page 26 ...

Page 26

... This is shown in Figure 15 on page 28 for each possible CAS latency; data element the last desired data element of a longer burst. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ ...

Page 27

... Figure 14: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK a, COL OUT OUT CLK READ NOP NOP BANK a, COL n D OUT CLK READ NOP NOP BANK a, COL 64Mb: x32 SDRAM ...

Page 28

... Figure 15: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK, COL OUT OUT CLK READ NOP NOP BANK, COL n D OUT CLK READ NOP NOP BANK, COL n ...

Page 29

... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18 on page 30. Data either the last of a burst of two or the last desired of a longer burst. This 64Mb SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture ...

Page 30

... Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until precharge will actually begin coincident with the clock-edge (T2 in Figure 21 “one- clock” (between T2 and T3 in Figure 21). PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK WRITE ...

Page 31

... PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Figure 19: Random WRITE Cycles COMMAND ADDRESS Note: Each WRITE command may be to any bank. DQM is LOW. Figure 20: WRITE-to-READ COMMAND ADDRESS PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK WRITE WRITE WRITE BANK, BANK, BANK, COL n ...

Page 32

... BA0 and BA1 are treated as “Don’t Care.” Aftera bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK ...

Page 33

... The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting Figure 22: Terminating a WRITE Burst COMMAND ADDRESS Note: DQMs are LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK BURST NEXT WRITE TERMINATE COMMAND ...

Page 34

... Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended (see examples in Figures 25 and 26 on page 35). PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN HIGH All Banks Bank Selected BANK ADDRESS DON’ ...

Page 35

... Clock Suspend During WRITE Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Figure 26: Clock Suspend During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP WRITE BANK, COL ...

Page 36

... Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...

Page 37

... Notes: 1. DQM is HIGH prevent D Figure 29: WRITE with Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Note: DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ READ - AP NOP NOP NOP BANK n READ with Burst of 4 Page Active BANK n, COL a D ...

Page 38

... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...

Page 39

... Table 9 and according to Table 10 on page 41. Precharging: Row activating: Read with auto precharge enabled: Write w/auto precharge enabled: PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN CAS# WE COMMAND INHIBIT (NOP/continue previous operation OPERATION (NOP/continue previous operation) ...

Page 40

... Starts with registration of an AUTO REFRESH command and ends t t when RC is met. After RC is met, the SDRAM will be in the all banks idle state. Starts with registration of a LOAD MODE REGISTER command and t ends when MRD has been met. After be in the all banks idle state ...

Page 41

... Write: Read w/auto precharge enabled: Write w/auto precharge enabled: 4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN CAS# WE COMMAND INHIBIT (NOP/continue previous operation OPERATION (NOP/continue previous operation) ...

Page 42

... WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to bank n will begin after tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 30 on page 38). PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ met, where WR begins when the WRITE to bank m is regis- Micron Technology, Inc ...

Page 43

... Storage temperature (plastic) Power dissipation Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 12 on page 44, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’ ...

Page 44

... For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots and the values should be viewed as typical. 3. These are estimates; actual results may vary. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Symbol ...

Page 45

... Figure 31: Example Temperature Test Point Location, 86-Pin TSOP (Top View) Test point Figure 32: Example Temperature Test Point Location, 90-Ball FBGA (Top View) Test point PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 22.22mm 11.11mm 8.00mm 4.00mm 13.00mm 6.50mm Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 46

... Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQs Table 17: VFBGA Capacitance Note 2 applies to entire table; notes appear on pages 49 and 50 Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQs PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Symbol ...

Page 47

... Refresh period (4,096 rows) Refresh period–Automotive (4,096 rows) PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time Write recovery time Exit self refresh to ACTIVE command PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ -55 Symbol Min Max Min Max t AC (3) – ...

Page 48

... Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst stop command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Symbol -5 -55 t CCD CKED ...

Page 49

... CLK must be toggled a minimum of two times during this period. 21. Based on 22 cannot be greater than one-third the cycle rate. V pulse width ≤ 3ns, and the pulse width cannot be greater than one-third the cycle rate. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ dependent on output loading and cycle rates. Specified values are obtained 40° ...

Page 50

... DD 28. Check factory for availability of specially screened devices having t CK for 100 MHz and slower ( PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ WR, and PRECHARGE commands). CKE may be used to reduce the (MIN) = 3.135V for -6, -55, and -5 speed grades 10ns and higher) in manual precharge. ...

Page 51

... ALL BA0, BA1 BANKS ( ( ) ) High 100µ (MIN) Power-up: V and Precharge DD CK stable all banks Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 2. Outputs are guaranteed High-Z after command is issued. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ ...

Page 52

... COMMAND PRECHARGE DQM 0-3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all active banks Note: Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CKS ( ( ) ) ( ...

Page 53

... READ NOP t CMS t CMH DQM0– A0–A9 COLUMN A10 BA0, BA1 BANK DQ Notes: 1. For this example and auto precharge is disabled and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP NOP NOP OUT OUT 64Mb: x32 SDRAM Timing Diagrams T6 ...

Page 54

... Figure 36: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0–3 A0–A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ AUTO NOP NOP NOP ( ( REFRESH ) ) ( ...

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... CMS t CMH COMMAND PRECHARGE DQM0–3 A0–A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes: 1. Self refresh mode not supported on automotive temperature (AT) devices. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CKS > t RAS ( ( ) ) ( ( ) ...

Page 56

... ROW ROW A10 BA0, BA1 BANK DQ Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP READ PRECHARGE t CMS t CMH COLUMN m 2 ALL BANKS SINGLE BANK ...

Page 57

... DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ is followed by a “manual” PRECHARGE and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK ...

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... AH A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ ...

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... ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK RCD - BANK 0 t RAS - BANK BANK 0 t RRD Notes: 1. For this example and and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ READ NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ROW BANK 0 BANK ...

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... ROW ROW A10 BA0, BA1 BANK BANK DQ t RCD Notes: 1. For this example and A9 = “Don’t Care.” 3. Page left open; no PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP NOP NOP t CMH Dout m D m+1 OUT t LZ 256 locations within same row ...

Page 61

... AH A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1. For this example and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ ...

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... BANK DQ t RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 10ns is required between <D to meet 3. A8 and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP WRITE NOP t CMS t CMH COLUMN m 3 ...

Page 63

... For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. Faster frequencies require two clocks (when 3. A8 and A9 = “Don’t Care.” CLK available if running 100 MHz or slower. Check factory for availability. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ WRITE ...

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... COLUMN m 3 ROW ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK RCD t RAS t RC Notes: 1. For this example Faster frequencies require two clocks (when 3. A8 and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP NOP NOP t CMH BANK ...

Page 65

... BA0, BA1 BANK RCD - BANK 0 t RAS - BANK BANK 0 t RRD Notes: 1. For this example Faster frequencies require two clocks (when 3. A8 and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ WRITE NOP ACTIVE NOP t CMH ROW ROW BANK 0 BANK 1 ...

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... CMH COMMAND ACTIVE NOP DQM 0 ROW A0- ROW A10 BA0, BA1 BANK DQ t RCD Notes and A9 = “Don’t Care.” must be satisfied prior to PRECHARGE command. 3. Page left open; no PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ WRITE NOP NOP t CMH t CMS COLUMN m 1 BANK ...

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... COMMAND ACTIVE DQM 0 A0-A9 ROW ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example and A9 = “Don’t Care.” PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ NOP WRITE NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK ...

Page 68

... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.025mm per side. 3. “2X” means the notch is present in two locations (both ends of the device). PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 0.61 2X 0.10 +0.07 -0.03 2X 2.80 11.76 ± ...

Page 69

... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 6.40 0.80 TYP ...

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