M29DW128G70NF6E NUMONYX, M29DW128G70NF6E Datasheet - Page 30

• Manufacturer Part Number: M29DW128G70NF6E
• Description: P7ED TSOP56 DUAL BANK
• Manufacturer: NUMONYX

Command interface
7.2
7.2.1
30/85
Fast program commands
The M29DW128G offers a set of fast program commands to improve the programming
throughput:
See
When V
bypass mode (see
After programming has started, bus read operations in the memory output the status
register content (bus reading operations from banks different from those including the block
being programmed, output the memory array content). Write to Buffer Program command
can be suspended and then resumed by issuing a Program Suspend command and a
Program Resume command, respectively (see
and
After the fast program operation has completed, the memory will return to the read mode,
unless an error has occurred. When an error occurs bus read operations to the memory will
continue to output the status register. A Read/Reset command must be issued to reset the
error condition and return to read mode. One of the erase commands must be used to set all
the bits in a block or in the whole memory from ’0’ to ’1’.
Typical program times are given in
endurance
Write to Buffer Program command
The Write to Buffer Program command makes use of the device’s 32-word write buffer to
speed up programming. 32 words can be loaded into the write buffer. Each write buffer has
the same A22-A5 addresses.The Write to Buffer Program command dramatically reduces
system programming time compared to the standard non-buffered Program command.
When issuing a Write to Buffer Program command, the V
V
See
Five successive steps are required to issue the Write to Buffer Program command:
1.
2.
3.
4.
5.
IH
, or raised to V
Section 7.1.9: Program Resume
Table 9: Fast program commands
Table 12
Write to Buffer Program
Enhanced Buffered Program
Unlock Bypass.
The Write to Buffer Program command starts with two unlock cycles
The third bus write cycle sets up the Write to Buffer Program command. The setup
code can be addressed to any location within the targeted block
The fourth bus write cycle sets up the number of words to be programmed. Value N is
written to the same block address, where N+1 is the number of words to be
programmed. N+1 must not exceed the size of the write buffer or the operation will
abort
The fifth cycle loads the first address and data to be programmed
Use N bus write cycles to load the address and data for each word into the write buffer.
Addresses must lie within the range from the start address+1 to the start address + N-
1. Optimum performance is obtained when the start address corresponds to a 32-word
PPH
cycles.
is applied to the V
for details on typical write to buffer program times in both cases.
PPH
Section 7.2.6: Unlock Bypass
.
PP
/write protect pin the memory automatically enters unlock
Table 12: Program, erase times and program, erase
command).
for a summary of the fast program commands.
Section 7.1.8: Program Suspend command
command).
PP
/WP pin can be either held High,
M29DW128G