ISPLSI 2032A-80LJN44 LATTICE SEMICONDUCTOR, ISPLSI 2032A-80LJN44 Datasheet

ISPLSI 2032A-80LJN44

Manufacturer Part Number

ISPLSI 2032A-80LJN44

Description

CPLD ispLSI® 2000A Family 1K Gates 32 Macro Cells 84MHz 0.35um (EECMOS) Technology 5V 44-Pin PLCC

Manufacturer

LATTICE SEMICONDUCTOR

Datasheet

1.ISPLSI_2032A-80LJ44.pdf (16 pages)

Specifications of ISPLSI 2032A-80LJN44

Package

44PLCC

Family Name

ispLSIÂ® 2000A

Device System Gates

1000

Maximum Propagation Delay Time

18.5 ns

Number Of User I/os

Number Of Logic Blocks/elements

Typical Operating Supply Voltage

5 V

Maximum Operating Frequency

84 MHz

Operating Temperature

0 to 70 Â°C

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• ENHANCEMENTS

• HIGH DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2032_11

Features

— ispLSI 2032A is Fully Form and Function Compatible

— ispLSI 2032A is Built on an Advanced 0.35 Micron

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

— Lead-Free Package Options

to the ispLSI 2032, with Identical Timing

Specifcations and Packaging

Machines, Address Decoders, etc.

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 180 MHz Maximum Operating Frequency

pd = 5.0 ns Propagation Delay

CMOS

Technology

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 2032 and 2032A are High Density Program-

mable Logic Devices. The devices contain 32 Registers,

32 Universal I/O pins, two Dedicated Input Pins, three

Dedicated Clock Input Pins, one dedicated Global OE

input pin and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2032 and 2032A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2032 and 2032A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1 .. A7

(Figure 1). There are a total of eight GLBs in the ispLSI

2032 and 2032A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram

Description

GLB

ispLSI

Global Routing Pool

Logic

Array

(GRP)

D Q

2032/A

August 2006

0139Bisp/2000

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ISPLSI 2032A-80LJN44 Summary of contents

Page 1

... Features • ENHANCEMENTS — ispLSI 2032A is Fully Form and Function Compatible to the ispLSI 2032, with Identical Timing Specifcations and Packaging — ispLSI 2032A is Built on an Advanced 0.35 Micron 2 ® E CMOS Technology • HIGH DENSITY PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2032/A Functional Block Diagram GOE 0 I I/O 2 I/O 3 I I/O 6 I/O 7 I/O 8 I I/O 11 I/O ...

Page 3

Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...

Page 4

... Typical values are and T = 25° Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2032/A Figure 2. Test Load GND to 3.0V ≤ ...

Page 5

External Timing Parameters 4 TEST 2 PARAMETER # COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Prop. Delay Clk Frequency with Internal Feedback max f – 4 Clk ...

Page 6

External Timing Parameters 4 TEST 2 PARAMETER # COND. t pd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock ...

Page 7

Internal Timing Parameters Over Recommended Operating Conditions 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc ...

Page 8

Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

Page 9

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 #42 GOE Derivations of su, h and co from the Product Term Clock ...

Page 10

Power Consumption Power consumption in the ispLSI 2032 and 2032A de- vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 120 ...

Page 11

Pin Description 44-PIN PLCC PIN NUMBERS NAME I I/O 3 15, 16, 17, 18, I I/O 7 22, 19, 20, 21, I I/O 11 25, 26, 27, 28, I I/O 15 29, ...

Page 12

Pin Configuration ispLSI 2032/A 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I VCC ispEN 1 SDI/IN 0 I/O 0 I Pins have dual function capability. ispLSI 2032/A 44-Pin TQFP Pinout Diagram ...

Page 13

Pin Configuration ispLSI 2032/A 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 VCC ispEN 2 SDI/IN 0 I/O 0 I pins are not to be connected to any active signal, ...

Page 14

... INDUSTRIAL ispLSI 2032A-80LJ44I 1 5 ispLSI 2032A-80LT44I 1 5 ispLSI 2032A-80LT48I 14 Grade ...

Page 15

... COMMERCIAL ORDERING NUMBER ispLSI 2032A-180LJN44 ispLSI 2032A-180LTN44 ispLSI 2032A-180LTN48 ispLSI 2032A-150LJN44 ispLSI 2032A-150LTN44 ispLSI 2032A-150LTN48 ispLSI 2032A-135LJN44 ispLSI 2032A-135LTN44 ispLSI 2032A-135LTN48 1 0 ispLSI 2032A-110LJN44 1 0 ispLSI 2032A-110LTN44 1 0 ispLSI 2032A-110LTN48 1 5 ispLSI 2032A-80LJN44 1 5 ispLSI 2032A-80LTN44 1 5 ispLSI 2032A-80LTN48 ...

Page 16

... Ordering Information (Cont.) Lead-Free Packaging Revision History Date Version — 10 August 2006 11 Specifications ispLSI 2032/A INDUSTRIAL ispLSI 2032A-80LJN44I 1 5 ispLSI 2032A-80LTN44I 1 5 ispLSI 2032A-80LTN48I Change Summary Previous Lattice release. Updated for lead-free package options Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP Lead-Free 48-Pin TQFP ...

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