ISPLSI 2032VE-110LTN44 LATTICE SEMICONDUCTOR, ISPLSI 2032VE-110LTN44 Datasheet
ISPLSI 2032VE-110LTN44
Specifications of ISPLSI 2032VE-110LTN44
Related parts for ISPLSI 2032VE-110LTN44
ISPLSI 2032VE-110LTN44 Summary of contents
Page 1
... N.E. Moore Ct. ...
Page 2
... The basic unit of logic on the ispLSI 2032VE device is the Generic Logic Block (GLB). The GLBs are labeled A0 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032VE device. Each GLB is made up of four macrocells ...
Page 3
... A2 A3 Generic Logic Blocks (GLBs) Clocks in the ispLSI 2032VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2 asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. ...
Page 4
... Input High Voltage IH Capacitance (T =25°C, f=1.0 MHz) A SYMBOL C Dedicated Input Capacitance 1 C I/O Capacitance 2 C Clock Capacitance 3 Erase Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispLSI 2032VE 1 PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A PARAMETER TYPICAL MINIMUM 10,000 3 MIN. MAX. ...
Page 5
... Refer to Power Consumption section CC of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Unused inputs 0V. IL Specifications ispLSI 2032VE Figure 2. Test Load GND to 3.0V ≤ 1.5 ns 1.5V 1.5V Device See Figure 2 ...
Page 6
... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2032VE Over Recommended Operating Conditions 1 DESCRIPTION tsu2 + tco1 ...
Page 7
... External Synchronous Clock Pulse Duration, Low 1. Unless noted otherwise, all parameters use a GRP load PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2032VE Over Recommended Operating Conditions 1 DESCRIPTION tsu2 + tco1 ...
Page 8
... Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2032VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...
Page 9
... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2032VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...
Page 10
... Note: Calculations are based on timing specifications for the ispLSI 2032VE-300L. Specifications ispLSI 2032VE GRP GLB Feedback Comb 4 PT Bypass #23 GRP Reg 4 PT Bypass GLB Reg Bypass #22 # XOR Delays #25, 26, 27 ...
Page 11
... I CC can be estimated for the ispLSI 2032VE using the following equation: For ispLSI 2032VE-300 and -225 (mA PTs * 1.29 nets * Fmax * 0.0068) For ispLSI 2032VE-180 and slower (mA PTs * 1.05 nets * Fmax * 0.0068) Where PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The I CC estimate is based on typical conditions ( ...
Page 12
... I I/O 20 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40 I/O 27 36, 37, 38, 41, 42, 43, 44 42, 43 pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2032VE Description 44-Pin PLCC 48-Pin TQFP ...
Page 13
... I VCC BSCAN TDI/IN 0 I/O 0 I pins are not to be connected to any active signals, VCC or GND. Pin Configuration ispLSI 2032VE 44-Pin PLCC Pinout Diagram (0.5in Lead Pitch/0.65 x 0.65in Body Size) I/O 28 I/O 29 I VCC BSCAN TDI/IN 0 I/O 0 I ...
Page 14
... TDI/IN 0 I/O 0 I Pins have dual function capability pins are not to be connected to any active signals, V Signal Configuration ispLSI 2032VE 49-Ball caBGA Signal Diagram (0.8mm Lead Pitch/7.0 x 7.0mm Body Size NCs are not to be connected to any active signals, VCC or GND. ...
Page 15
... MHz max f 225 = 225 MHz max f 180 = 180 MHz max f 135 = 135 MHz max f 110 = 110 MHz max ispLSI 2032VE Ordering Information Conventional Packaging FAMILY fmax (MHz) tpd (ns) 300 300 300 225 225 225 225 180 180 180 ispLSI ...
Page 16
... INDUSTRIAL ORDERING NUMBER 5.0 ispLSI 2032VE-180LTN44I Previous Lattice release. Updated for 48-pin TQFP lead-free package option. 15 PACKAGE Lead-Free 44-Pin TQFP ...