XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 10

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Revision History
This section records the change history for this module of the data sheet.
DS083 (v4.7) November 5, 2007
Product Specification
01/31/02
06/13/02
09/03/02
09/27/02
11/20/02
01/20/03
03/24/03
08/25/03
12/10/03
02/19/04
03/09/04
06/30/04
11/17/04
03/01/05
06/20/05
09/15/05
10/10/05
03/05/07
11/05/07
Date
R
Version
2.4.1
2.4.2
3.1.1
1.0
2.0
2.1
2.2
2.3
2.4
3.0
3.1
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Initial Xilinx release.
New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
Updates to
In
Add bullet items for 3.3V I/O features.
Merged in DS110-1 (Module 1 of Virtex-II Pro X data sheet). Added information on available
Pb-free packages.
No changes in Module 1 for this revision.
Table
No changes in Module 1 for this revision.
No changes in Module 1 for this revision.
Updated copyright notice and legal disclaimer.
Table
In
Remove FF1517 package option for XC2VP40.
Correct number of single-ended I/O standards from 19 to 22.
Correct minimum RocketIO serial speed from 622 Mbps to 600 Mbps.
Add footnote referring to XAPP659 to callout for 3.3V I/O standards on page 4.
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
Figure
Recompiled for backward compatibility with Acrobat 4 and above. No content
changes.
Changed all instances of 10.3125 Gb/s (RocketIO transceiver maximum bit rate) to
Changed XC2VPX70 variable baud rate specification to fixed-rate operation at
-5 and -6, are released to Production status.
Table
Section
differential standards supported from six to ten.
Section
available for LVDS, LVDS Extended, ULVDS, and LDT standards.
6.25 Gb/s.
Changed all instances of 412.5 Gb/s (RocketIO X transceiver maximum multi-channel
raw data transfer rate) to 250 Gb/s.
4.25 Gb/s.
Changed maximum performance for -7 Virtex-II Pro X MGT
3: Corrected number of RocketIO transceivers for XC2VP7-FG456.
Table
1, correct max number of XC2VP30 I/Os to 644.
1: Corrected number of RocketIO transceiver blocks for XC2VP40.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
1: Added note stating that -7 devices are not available in Industrial grade.
Table 1
3, add FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
Virtex-II Pro Platform FPGA Technology (All
Input/Output Blocks
and
www.xilinx.com
Table
3. Processor Block information added to
(IOBs): Added text stating that differential termination is
Revision
Devices): Updated number of
(Table
Table
4) to N/A.
4.
Module 1 of 4
9

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