XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 100

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 36
Table 36: Input Delay Measurement Methodology
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
5.
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I & II
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Tnscvr Logic), Class I & II, 2.5V
SSTL, Class I & II, 1.8V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
ULVDS (Ultra LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V
Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
listed are typical. See
Input voltage level from which measurement starts.
Note that this is an input voltage reference that bears no relation to the V
shows the test setup parameters used for measuring Input standard adjustments (see
R
Description
Virtex-II Pro Platform FPGA User Guide
L
and V
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
H
.
www.xilinx.com
REF
HSTL_III_18, HSTL_IV_18
for min/max specifications.
HSTL_I_18, HSTL_II_18
values. Reported delays reflect worst case of these measurements. V
SSTL18_I, SSTL18_II
HSTL_III, HSTL_IV
SSTL2_I, SSTL2_II
HSTL_I, HSTL_II
IOSTANDARD
LVDSEXT_25
LVPECL_25
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
REF
ULVDS_25
Attribute
LVDS_25
PCI33_3
PCI66_3
LDT_25
LVTTL
GTLP
PCIX
GTL
/ V
MEAS
parameters found in IBIS models and/or noted in
V
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
V
V
V
V
V
V
V
1.15 – 0.3
REF
REF
REF
REF
REF
REF
REF
REF
V
L
0
0
0
0
0
– 0.75
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
(1,2)
Per PCI-X Specification
Per PCI Specification
Per PCI Specification
V
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
V
V
V
V
V
V
V
1.15 + 0.3
Table 33, page
REF
REF
REF
REF
REF
REF
REF
REF
V
3.3
3.3
2.5
1.8
1.5
H
+ 0.75
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
(1,2)
V
(1,4,5)
V
V
V
V
V
V
V
V
1.65
1.65
1.25
0.75
1.15
MEAS
0.9
1.2
1.2
0.6
0.6
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
23).
Figure
REF
(1,3,5)
V
values
0.80
0.75
0.90
0.90
1.08
1.25
1.0
0.9
REF
6.
29

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