XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 103

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Clock Distribution Switching Characteristics
Table 38: Clock Distribution Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see
are worst-case. Precise values are provided by the timing analyzer.
Table 39: CLB Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
Global Clock Buffer I input to O output
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
Combinatorial Delays
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Set/Reset
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to
XQ/YQ outputs
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum Pulse Width, SR/BY inputs (asynchronous)
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (for export control)
if a “0” is listed, there is no positive hold time.
R
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
T
T
T
T
T
DXCK
CECK
DYCK
T
DICK
Symbol
Symbol
T
RCK/
T
GSI
T
T
T
SOPSOP
T
T
T
T
F
IFNCTL
T
T
T
INAFX
INBFX
T
T
CKLO
T
IFXY
RPW
IF5X
CKO
TOG
GIO
ILO
RQ
IF5
CH
CL
/T
/T
/T
/T
/T
T
GIS
CKDI
CKDY
CKDX
CKCE
CKR
0.49/–0.10
0.21/–0.04
0.55/–0.01
0.00/ 0.12
0.00/ 0.12
0.27/ 0.01
Figure 34
1350
0.05
0.28
0.59
0.63
0.29
0.29
0.29
0.11
0.23
0.37
0.54
0.37
0.37
0.37
1.09
-7
-
7
Speed Grade
in Module 2). The values listed below
Speed Grade
0.54/–0.12
0.24/–0.05
0.60/–0.01
0.00/ 0.14
0.00/ 0.14
0.34/ 0.01
0.057
1200
0.32
0.65
0.70
0.32
0.32
0.32
0.13
0.24
0.38
0.57
0.40
0.40
0.40
1.25
-6
-
6
0.60/–0.13
0.27/–0.06
0.78/–0.01
0.00/ 0.15
0.00/ 0.15
0.47/ 0.01
0.064
1050
0.36
0.73
0.79
0.36
0.36
0.36
0.14
0.27
0.42
0.64
0.45
0.45
0.45
1.40
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
MHz
32

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