XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 116

no-image

XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP7-5FF672C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC2VP7-5FF672C
Manufacturer:
XILINX
0
Part Number:
XC2VP7-5FF672C
Manufacturer:
ALTERA
0
Company:
Part Number:
XC2VP7-5FF672C
Manufacturer:
XILINX
Quantity:
1 582
Part Number:
XC2VP7-5FF672C (TRAY)
Manufacturer:
XILINX
0
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
Operating Frequency Ranges
e
Table 54: Operating Frequency Ranges
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5%
5. CLK2X and CLK2X180 may not be used as the input to the CLKFB pin. See the
6. For the XC2VP100 -6 device only, clock macros for corner DCMS (X0Y0, X5Y0, X0Y1, X5Y1) are required to operate at maximum
Output Clocks (Low Frequency Mode)
Input Clocks (Low Frequency Mode)
Output Clocks (High Frequency Mode)
Input Clocks (High Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
PSCLK
CLK0, CLK180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
PSCLK
(45/55 to 55/45).
information.
clock frequency. See
Description
R
(6)
(5,6)
XAPP685
(1,3,4)
(1,3,4,6)
(2,3,4)
(2,3,4)
for implementation examples.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CLKOUT_FREQ_1X_LF_MIN
CLKOUT_FREQ_1X_LF_MAX
CLKOUT_FREQ_2X_LF_MIN
CLKOUT_FREQ_2X_LF_MAX
CLKOUT_FREQ_DV_LF_MIN
CLKOUT_FREQ_DV_LF_MAX
CLKOUT_FREQ_FX_LF_MIN
CLKOUT_FREQ_FX_LF_MAX
CLKIN_FREQ_DLL_LF_MIN
CLKIN_FREQ_DLL_LF_MAX
CLKIN_FREQ_FX_LF_MIN
CLKIN_FREQ_FX_LF_MAX
PSCLK_FREQ_LF_MIN
PSCLK_FREQ_LF_MAX
CLKOUT_FREQ_1X_HF_MIN
CLKOUT_FREQ_1X_HF_MAX
CLKOUT_FREQ_DV_HF_MIN
CLKOUT_FREQ_DV_HF_MAX
CLKOUT_FREQ_FX_HF_MIN
CLKOUT_FREQ_FX_HF_MAX
CLKIN_FREQ_DLL_HF_MIN
CLKIN_FREQ_DLL_HF_MAX
CLKIN_FREQ_FX_HF_MIN
CLKIN_FREQ_FX_HF_MAX
PSCLK_FREQ_HF_MIN
PSCLK_FREQ_HF_MAX
Symbol
www.xilinx.com
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Constraints
Virtex-II Pro Platform FPGA User Guide
270.00
450.00
140.00
240.00
270.00
240.00
450.00
450.00
280.00
210.00
320.00
450.00
320.00
450.00
-7
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
Speed Grade
210.00
420.00
140.00
240.00
210.00
240.00
420.00
420.00
280.00
210.00
320.00
420.00
320.00
420.00
-6
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
180.00
360.00
120.00
210.00
180.00
210.00
360.00
360.00
240.00
210.00
270.00
360.00
270.00
360.00
-5
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
Module 3 of 4
for more
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
45

Related parts for XC2VP7-5FF672C