XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 120

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro
source-synchronous transmitter and receiver data-valid windows.
Table 61: Duty Cycle Distortion and Clock-Tree Skew
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
Duty Cycle Distortion
Clock Tree Skew
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T
used to provide the negative-edge clock to the DDR element in the I/O. Users must follow the implementation guidelines contained
in
T
in the I/O.
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DCD_LOCAL
DCD_CLK180
XAPP685
Description
R
applies to cases where the dedicated path from the DCM to the BUFG is bypassed and where local (IOB) inversion is
for these specifications to apply.
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
(2)
(1)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
DCD_CLK180
DCD_LOCAL
Symbol
T
CKSKEW
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XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
All
0.10
0.10
0.13
0.13
0.13
0.20
0.20
0.20
0.33
0.40
0.54
0.54
N/A
7
Speed Grade
0.10
0.11
0.13
0.13
0.13
0.21
0.21
0.22
0.34
0.41
0.59
0.59
0.79
6
0.20
0.13
0.13
0.13
0.13
0.22
0.22
0.24
0.35
0.42
0.64
0.64
0.87
5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49

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