XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 126

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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DS083 (v4.7) November 5, 2007
Product Specification
12/05/03
02/19/04
03/09/04
04/22/04
06/30/04
(cont’d)
Date
R
Version
(cont’d)
3.1.1
3.0
3.1
3.2
4.0
Merged in DS110-3 (Module 3 of Virtex-II Pro X data sheet). This merge added numerous
previously unpublished RocketIO X MGT parameters. Specifications in this revision are
from speedsfile v1.86.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Non-speedsfile parameter values added or updated:
Table
Table
Table
Updated time and frequency parameters as per speedsfile v1.85.
Table
Table
parameters.
Table
Differential Input Voltage (LVPECL).
Table
designs for which test data is no longer provided.
Table
to XAPP755.
Added
Revised section
Recompiled for backward compatibility with Acrobat 4 and above. No content
Table
Table
Table
Table
Access Port Switching Characteristics, page
parameter tables, and organization.
Table
Mode Write Timing
Table
DATA[0:7] setup/hold time, by device, and added new parameter specifications for
XC2VP70 and XC2VP100 devices.
Table
four CLKIN parameters. Added new Footnote (4) to the four CLKIN parameters. Added
new Footnote (5) to CLK2X, CLK2X180. Added new Footnote (6) to CLK2X,
CLK2X180; CLK0, CLK180; and CLKIN (using DLL outputs).
changes.
Table
limit from 1.8V to 1.6V.
Table
listed I
1.4V to 1.65V.
Table
CLKIN_FREQ_DLL_LF_MAX for -7 devices from 210 MHz to 270 MHz.
Table
3: I
4: For XC2VP100, I
5: For XC2VP100, I
17: T
25: Added explanatory footnote to T
54: Added Footnote (3) regarding use of CLKIN_DIVIDE_BY_2 attribute.
2,
4,
10,
14,
16,
47,
48,
54,
2,
5,
37,
54,
62,
CCOMIN
Table
Recommended Operating
Quiescent Supply
Recommended Operating
Power-On Current for Virtex-II Pro
BATT
Operating Frequency
LVPECL DC
Register-to-Register
Processor Clocks Absolute AC
Master/Slave Serial Mode Timing
SelectMAP Mode Write Timing
Operating Frequency
Output Delay Measurement
Package
CPWL
38,
.
values apply to the entire device (all banks).
Configuration Timing, page 37
Clock Distribution Switching
and T
www.xilinx.com
Skew: Removed XC2VP40FF1517.
Characteristics: Added parameter F
CPWH
Specifications: Added parameter values for Maximum
CCINTQ
CCINTMIN
Current: Added Footnote (1) and updated Typical
.
Performance: Removed reference to a number of
Ranges: Corrected CLKOUT_FREQ_1X_LF_MAX and
Ranges: Added callouts for existing Footnote (3) to the
, I
CCOQ
.
Conditions: Revised Footnotes (4) and (6).
Conditions: Corrected VTTX/VTRX lower voltage
Revision
Methodology: Corrected V
, and I
Characteristics: Added Footnote (1) referring
Characteristics: Broke out T
RXLAT
Devices: Added Footnote (2) stating that
Characteristics, and
40, with improved timing diagrams,
Characteristics.
CCAUXQ
through
(MGT receiver latency) max value.
.
CC_STARTUP
page
39, and
MEAS
Table
.
SMDCC
JTAG Test
for LVTTL from
48,
SelectMAP
Module 3 of 4
/T
SMCCD
,
55

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