XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 19

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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0
ing character, and remembers its location in the buffer. At
some point, one transceiver designated as the master
instructs all the transceivers to align to the channel bonding
character "P" (or to some location relative to the channel
bonding character).
After this operation, words transmitted to the FPGA fabric
are properly aligned: RRRR, SSSS, TTTT, and so forth, as
shown in the bottom-right portion of
the channels remain properly aligned following the channel
bonding operation, the master transceiver must also control
the clock correction operations described in the previous
section for all channel-bonded transceivers.
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is fre-
quency-locked to its read pointer (REFCLK). Therefore,
clock correction and channel bonding are not required. The
purpose of the transmitter's buffer is to accommodate a
phase difference between TXUSRCLK and REFCLK. A
simple FIFO suffices for this purpose. A FIFO depth of four
will permit reliable operation with simple detection of over-
flow or underflow, which could occur if the clocks are not fre-
quency-locked.
DS083 (v4.7) November 5, 2007
Product Specification
R
Figure
7. To ensure that
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
www.xilinx.com
RocketIO X Configuration
This section outlines functions that can be selected or con-
trolled by configuration. Xilinx implementation software sup-
ports the transceiver primitives shown in
Table 3: Supported RocketIO X Transceiver Primitives
Full word SSSS sent over four channels, one byte per channel
GT10_CUSTOM
GT10_OC48_1
GT10_OC48_2
GT10_OC48_4
GT10_PCI_EXPRESS_1
GT10_PCI_EXPRESS_2
GT10_PCI_EXPRESS_4
GT10_INFINIBAND_1
GT10_INFINIBAND_2
GT10_INFINIBAND_4
Before channel bonding
Primitive
P Q R S T
Figure 7: Channel Bonding (Alignment)
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
RXUSRCLK
Read
In Transmitters:
In Receivers:
Fully customizable by user
SONET OC-48, 1-byte data path
SONET OC-48, 2-byte data path
SONET OC-48, 4-byte data path
PCI Express, 1-byte data path
PCI Express, 2-byte data path
PCI Express, 4-byte data path
Infiniband, 1-byte data path
Infiniband, 2-byte data path
Infiniband, 4-byte data path
Channel (lane) 0
Channel (lane) 1
Channel (lane) 2
Channel (lane) 3
Description
After channel bonding
Table
P Q R S T
RXUSRCLK
P Q R S T
P Q R S T
P Q R S T
Read
3.
Module 2 of 4
DS083-2_16_010202
8

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