XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 2

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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DS083 (v4.7) November 5, 2007
Summary of Virtex-II Pro™ / Virtex-II Pro X Features
Table 1: Virtex-II Pro / Virtex-II Pro X FPGA Family Members
RocketIO X Transceiver Features (XC2VPX20 and XC2VPX70 Only)
© 2002–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
Device
-7 speed grade devices are not available in Industrial grade.
Logic Cell ≈ (1) 4-input LUT + (1)FF + Carry Logic
These devices can be ordered in a configuration without RocketIO transceivers. See
Virtex-II Pro X devices equipped with RocketIO X transceiver cores.
High-Performance Platform FPGA Solution, Including
-
-
Based on Virtex-II™ Platform FPGA Technology
-
-
-
Variable-Speed Full-Duplex Transceiver (XC2VPX20)
Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates.
-
Fixed-Speed Full-Duplex Tranceiver (XC2VPX70)
Operating at 4.25 Gb/s Baud Transfer Rate.
Eight or Twenty Transceiver Modules on an FPGA,
Depending upon Device
Monolithic Clock Synthesis and Clock Recovery
-
Up to twenty RocketIO™ or RocketIO X embedded
Multi-Gigabit Transceivers (MGTs)
Up to two IBM PowerPC™ RISC processor blocks
Flexible logic resources
SRAM-based in-system configuration
Active Interconnect technology
Includes specific baud rates used by various
standards, as listed in
Eliminates the need for external components
(1)
Transceiver
0
RocketIO
(3)
0
0
16 or 20
Blocks
(3)
(3)
, 8, or 12
20
4
4
8
8
8
8
or 16
or 20
(4)
(4)
Processor
PowerPC
Blocks
R
Table 4, Module
0
1
1
2
1
2
2
2
2
2
2
1
0
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
11,088
20,880
22,032
30,816
43,632
53,136
74,448
74,448
99,216
Logic
Cells
3,168
6,768
(2)
2.
CLB (1 = 4 slices =
13,696
19,392
23,616
33,088
33,088
44,096
Slices
1,408
3,008
4,928
9,280
9,792
www.xilinx.com
max 128 bits)
Max Distr
RAM (Kb)
1,034
1,034
1,378
154
290
306
428
606
738
Virtex-II Pro / Virtex-II Pro X family members and resources
are shown in
44
94
-
-
-
-
-
Automatic Lock-to-Reference Function
Programmable Serial Output Differential Swing
-
-
Programmable Pre-emphasis Levels 0 to 500%
Telecom/Datacom Support Modes
-
-
18 X 18 Bit
SelectRAM™+ memory hierarchy
Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectI/O™-Ultra technology
XCITE Digitally Controlled Impedance (DCI) I/O
200 mV to 1600 mV, peak-peak
Allows compatibility with other serial system
voltage levels
"x8" and "x10" clocking/data paths
64B/66B clocking support
Table 3
Multiplier
Blocks
136
192
232
328
308
444
Introduction and Overview
12
28
44
88
88
Table
for package configurations.
1.
Blocks
Block SelectRAM+
18 Kb
136
192
232
328
308
444
12
28
44
88
88
Max Block
RAM (Kb)
1,584
1,584
2,448
3,456
4,176
5,904
5,544
7,992
216
504
792
Product Specification
DCMs
12
4
4
4
8
8
8
8
8
8
8
Module 1 of 4
Maximum
I/O Pads
1,164
User
204
348
396
564
552
644
804
852
996
992
1

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