XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 22

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Output Swing and Pre-emphasis
The output swing and pre-emphasis levels of the RocketIO
MGTs are fully programmable. Each is controlled via
attributes at configuration, but can be modified via partial
reconfiguration.
The programmable output swing control can adjust the dif-
ferential output level between 400 mV and 800 mV in four
increments of 100 mV.
DS083 (v4.7) November 5, 2007
Product Specification
PACKAGE
AVCCAUXRX
AVCCAUXTX
R
PINS
GNDA
VTRX
VTTX
RXP
RXN
TXN
TXP
2.5V RX
Termination Supply RX
TX/RX GND
2.5V TX
Termination Supply TX
Deserializer
Manager
Serializer
Clock
Figure 10: RocketIO Transceiver Block Diagram
MULTI-GIGABIT TRANSCEIVER CORE
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Power Down
Polarity
Output
Comma
Realign
Detect
www.xilinx.com
FIFO
With pre-emphasis, the differential voltage swing is boosted
to create a stronger rising waveform. This method compen-
sates for high-frequency loss in the transmission media that
would otherwise limit the magnitude of this waveform. Lossy
transmission lines cause the dissipation of electrical energy.
This pre-emphasis technique extends the distance that sig-
nals can be driven down lossy line media and increases the
signal-to-noise ratio at the receiver.
Decoder
8B/10B
TX
Channel Bonding
Clock Correction
Encoder
8B/10B
and
Check
Elastic
Buffer
CRC
RX
CRC
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
ENPCOMMAALIGN
ENMCOMMAALIGN
RXCHECKINGCRC
RXCRCERR
RXDATA[15:0]
RXDATA[31:16]
RXNOTINTABLE[3:0]
RXDISPERR[3:0]
RXCHARISK[3:0]
RXCHARISCOMMA[3:0]
RXRUNDISP[3:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
CHBONDDONE
CHBONDI[3:0]
CHBONDO[3:0]
RXLOSSOFSYNC
RXCLKCORCNT
TXBUFERR
TXFORCECRCERR
TXDATA[15:0]
TXDATA[31:16]
TXBYPASS8B10B[3:0]
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
TXKERR[3:0]
TXRUNDISP[3:0]
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
RXRESET
REFCLK
BREFCLK
BREFCLK2
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
REFCLK2
REFCLKSEL
FPGA FABRIC
DS083-2_04_090402
Module 2 of 4
11

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