XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 4

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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General Description
The Virtex-II Pro and Virtex-II Pro X families contain plat-
form FPGAs for designs that are based on IP cores and
customized modules. The family incorporates multi-gigabit
transceivers and PowerPC CPU blocks in Virtex-II Pro
Series FPGA architecture. It empowers complete solutions
for telecommunication, wireless, networking, video, and
DSP applications.
The leading-edge 0.13 µm CMOS nine-layer copper pro-
cess and Virtex-II Pro architecture are optimized for high
performance designs in a wide range of densities. Combin-
ing a wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
Architecture
Array Overview
Virtex-II Pro and Virtex-II Pro X devices are user-program-
mable gate arrays with various configurable elements and
embedded blocks optimized for high-density and high-per-
formance system designs. Virtex-II Pro devices implement
the following functionality:
DS083 (v4.7) November 5, 2007
Product Specification
-
SRAM-Based In-System Configuration
-
-
-
-
-
Embedded high-speed serial transceivers enable data
bit rate up to 3.125 Gb/s per channel (RocketIO) or
6.25 Gb/s (RocketIO X).
Embedded IBM PowerPC 405 RISC processor blocks
provide performance up to 400 MHz.
SelectIO-Ultra blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported
by the programmable IOBs.
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
·
·
Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
·
·
·
Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security
option (bitstream encryption)
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
R
HyperTransport (LDT) I/O with current driver
buffers
Built-in DDR input and output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
www.xilinx.com
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all these ele-
ments. The general routing matrix (GRM) is an array of rout-
ing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and supports high-speed designs.
All
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Features
This section briefly describes Virtex-II Pro / Virtex-II Pro X
features. For more details, refer to
Virtex-II Pro X Platform FPGAs: Functional
RocketIO / RocketIO X MGT Cores
The RocketIO and RocketIO X Multi-Gigabit Transceivers
are flexible parallel-to-serial and serial-to-parallel embed-
ded transceiver cores used for high-bandwidth interconnec-
tion between buses, backplanes, or other subsystems.
Multiple user instantiations in an FPGA are possible,
providing
(RocketIO X) of full-duplex raw data transfer. Each channel
can be operated at a maximum data transfer rate of
3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X).
-
Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
-
-
0.13 µm Nine-Layer Copper Process with 90 nm
High-Speed Transistors
1.5V (V
V
IEEE 1149.1 Compatible Boundary-Scan Logic Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch.
Wire-Bond BGA Devices Available in Pb-Free
Packaging
Each Device 100% Factory Tested
Block SelectRAM+ memory modules provide large
18 Kb storage elements of True Dual-Port RAM.
Embedded multiplier blocks are 18-bit x 18-bit
dedicated multipliers.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, and coarse- and fine-grained clock phase
shifting.
programmable
CCAUX
Readback capability
Integrated VHDL and Verilog design flows
ChipScope™ Integrated Logic Analyzer
CCINT
up
auxiliary and V
(www.xilinx.com/pbfree)
to
) core power supply, dedicated 2.5V
100 Gb/s
elements,
CCO
I/O power supplies
(RocketIO)
including
Virtex-II Pro and
Description.
or
the
Module 1 of 4
170 Gb/s
routing
3

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