XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 49

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Figure
ple configurations.
DS083 (v4.7) November 5, 2007
Product Specification
WCLK
A[3:0]
A[4]
WE
Figure 36: Distributed SelectRAM+ (RAM16x1S)
WCLK
Figure 37: Single-Port Distributed SelectRAM+
D
A[3:0]
WE
36,
D
(BX)
(BY)
(SR)
Figure
4
(BY)
(SR)
R
4
4
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
37, and
WS
RAM 32x1S
WE0
WE
CK
G[4:1]
WG[4:1]
F[4:1]
WF[4:1]
WSF
RAM
WS
WS
WSG
RAM
RAM
(RAM32x1S)
DI
DI
DI
Figure 38
D
D
D
F5MUX
(optional)
illustrate various exam-
D
Q
(optional)
D
DS031_02_100900
Q
Output
Registered
Output
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DS083-2_10_050901
Output
Registered
Output
www.xilinx.com
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.
number of LUTs occupied by each configuration.
Table 17: ROM Configuration
DPRA[3:0]
Figure 38: Dual-Port Distributed SelectRAM+
available:
WCLK
A[3:0]
A[3:0]
WE
128 x 1
256 x 1
D
16 x 1
32 x 1
64 x 1
ROM
(SR)
(BY)
4
ROM16x1,
4
4
(RAM16x1D)
RAM 16x1D
WE
CK
WE
CK
G[4:1]
WG[4:1]
G[4:1]
WG[4:1]
WSG
WSG
WS
WS
dual_port
RAM
dual_port
RAM
ROM32x1,
DI
DI
Number of LUTs
D
D
Table 17
16 (2 CLBs)
8 (1 CLB)
DS031_04_110100
1
2
4
Module 2 of 4
shows the
ROM64x1,
SPO
DPO
38

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