XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 63
Manufacturer Part Number
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Specifications of XC2VP7-5FF672C
Device Logic Units
Number Of Registers
Maximum Internal Frequency
Typical Operating Supply Voltage
Maximum Number Of User I/os
The DCM has the following general control signals:
Table 27: DCM Status Pins
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
To achieve clock de-skew, connect the CLKFB input to
CLK0. Note that CLKFB must always be connected, unless
only the CLKFX or CLKFX180 outputs are used and
de-skew is not required.
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
where M and D are two integers. Specifications for M and D
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and
DS083 (v4.7) November 5, 2007
LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
STATUS output pins (active High): shown in
Characteristics. By default, M = 4 and D = 1,
resets the entire DCM
Phase Shift Overflow
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
which results in a clock output frequency four times faster
than the clock input frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles, with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode.
Note that CLK2X and CLK2X180 are not available in
Table 28: CLKDV Duty Cycle for Non-integer Divides
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
In variable mode, the
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.
shifting. For more information on DCM features, see the
Virtex-II Pro Platform FPGA User Guide.
Table 29: Fine Phase Shifting Control Pins
lists fine-phase shifting control pins, when used in
for more details.
illustrates the effects of fine-phase
Increment or decrement
Enable ± phase shift
Clock for phase shift
Active when completed
value can also be
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Module 2 of 4