XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 7

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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implemented. In system mode, a Virtex-II Pro device will
continue to function while executing non-test Bound-
ary-Scan instructions. In test mode, Boundary-Scan test
instructions control the I/O pins for testing purposes. The
Virtex-II Pro Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II Pro / Virtex-II Pro devices are configured by load-
ing the bitstream into internal configuration memory using
one of the following modes:
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration data.
The Xilinx System Advanced Configuration Enviornment
(System ACE) family offers high-capacity and flexible solu-
tion for FPGA configuration as well as program/data storage
for the processor. See
Solution for more information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II Pro / Virtex-II Pro con-
figuration memory can be read back for verification. Along
with the configuration data, the contents of all flip-flops and
latches, distributed SelectRAM+, and block SelectRAM+
memory resources can be read back. This capability is use-
ful for real-time debugging.
DS083 (v4.7) November 5, 2007
Product Specification
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532)
R
DS080
, System ACE CompactFlash
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
www.xilinx.com
The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores
and Integrated Bus Analyzer (IBA) cores, along with the
ChipScope Pro Analyzer software, provide a complete solu-
tion for accessing and verifying user designs within
Virtex-II Pro devices.
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution.
In addition to the existing FPGA fabric cores, the list below
shows some of the currently available hardware and soft-
ware intellectual properties
Virtex-II Pro / Virtex-II Pro X by Xilinx. Each IP core is mod-
ular, portable, Real-Time Operating System (RTOS) inde-
pendent, and CoreConnect compatible for ease of design
migration. Refer to
and most complete list of cores.
Hardware Cores
Software Cores
Bus Infrastructure cores (arbiters, bridges, and more)
Memory cores (DDR, Flash, and more)
Peripheral cores (UART, IIC, and more)
Networking cores (ATM, Ethernet, and more)
Boot code
Test code
Device drivers
Protocol stacks
RTOS integration
Customized board support package
www.xilinx.com/ipcenter
specially
developed
for the latest
Module 1 of 4
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