XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 85

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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RocketIO Switching Characteristics
Table 22: RocketIO X Reference Clock Switching Characteristics
Table 23: RocketIO Reference Clock Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
Notes:
1.
2.
3.
4.
Reference Clock frequency range
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Clock recovery frequency acquisition time,
from Power-up to High state of PMARXLOCK
Clock recovery phase acquisition time,
from Data to High state of PMARXLOCK
Reference Clock frequency range
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Clock recovery frequency acquisition time
Clock recovery phase acquisition time
BREFCLK should be used for all serial bit rates up to the maximum shown.
BREFCLK/BREFCLK2 can be used for all serial bit rates up to the maximum shown. REFCLK/REFCLK2 can be used for serial bit rates up to
2.5 Gb/s (REFCLK = 125 MHz). All other parameters apply equally to REFCLK, REFCLK2, BREFCLK, and BREFCLK2 except as noted.
For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in
receive jitter tolerance specifications defined in this data sheet.
Measured at the package pin. For reference clock frequencies equal to or above 125 MHz, BREFCLK/BREFCLK2 must be used.
8B/10B-type bitstream.
R
Description
Description
80%
20%
T
(1)
(1)
FCLK
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
(3)
Figure 3: Reference Clock Timing Parameters
Symbol
Symbol
T
T
T
T
F
F
T
F
T
T
T
T
F
T
T
T
DCREF
PHASE
DCREF
PHASE
GCLK
GTOL
LOCK
GCLK
GTOL
LOCK
RCLK
FCLK
RCLK
FCLK
GJTT
GJTT
www.xilinx.com
T
RCLK
2.488 Gb/s – 3.125 Gb/s
2.501 Gb/s – 3.125 Gb/s
3.125 Gb/s – 6.25 Gb/s
1.061 Gb/s – 2.5 Gb/s
Half rate operation
(2X oversampling)
Full rate operation
Conditions
Conditions
< 1.06 Gb/s
20% – 80%
20% – 80%
20% – 80%
20% – 80%
XAPP572
(2)
62.5
Min
Min
are required to meet the transmit jitter and
45
50
60
45
All Speed Grades
All Speed Grades
DS083-3_01_120302
Typ
Typ
100
600
600
960
75
75
50
40
50
156.25
±350
±100
1000
1000
Max
Max
425
100
120
55
30
40
60
55
40
50
10
Module 3 of 4
Units
Units
MHz
MHz
MHz
ppm
ppm
bits
ps
ps
ps
ps
µs
µs
ps
ps
ps
ps
µs
ps
%
%
(4)
14

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