XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 86

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Table 24: RocketIO X Receiver Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
2.
3.
4.
Receive total jitter tolerance
using default equalization and PRBS-15
pattern
Receive random jitter tolerance
Receive sinusoidal jitter tolerance
measured at 70 MHz
Receive deterministic jitter tolerance
Receive latency
RXUSRCLK duty cycle
RXUSRCLK2 duty cycle
Differential receive input sensitivity
UI = Unit Interval
Receive latency delay RXP/RXN to RXDATA. Refer to
This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both
disabled, the maximum will be near the typical values.
R
Description
(3)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Symbol
T
T
T
T
T
T
T
V
RX2DC
RJTOL
SJTOL
DJTOL
RXLAT
RXDC
JTOL
EYE
RocketIO X Transceiver User Guide
www.xilinx.com
Conditions
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
(1)
Min
45
45
for more information on calculating latency.
0.80
0.80
0.80
0.80
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.55
0.55
0.55
0.50
Typ
120
25
50
50
Max
0.65
0.65
0.65
0.65
0.15
0.15
0.15
0.15
0.45
0.45
0.45
0.45
250
34
55
55
(4)
RXUSRCLK cycles
Units
Module 3 of 4
mV
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
%
%
(2)
15

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