XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 88

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Table 26: RocketIO X Transmitter Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
5.
Serial data rate
Serial data output total jitter (p-p)
Serial data output deterministic jitter (p-p)
Serial data output random jitter (p-p)
TX rise time
TX fall time
Transmit latency
TXUSRCLK duty cycle
TXUSRCLK2 duty cycle
The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
UI = Unit Interval
Total Jitter T
T
BER=10
Transmit latency delay TXDATA to TXP/TXN. Refer to
RJ
specifications are wideband and include low-frequency jitter components (also referred to as wander).T
–12
R
using the Bathtub Method.
TJ
(5)
= T
Description
DJ
+ T
RJ
(3)
(3,4)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
(3)
Symbol
T
RocketIO X Transceiver User Guide
T
T
F
T
T
TX2DC
TXLAT
T
T
TXDC
T
GTX
RTX
FTX
DJ
RJ
TJ
www.xilinx.com
@ 2.500 Gb/s
Conditions
20% – 80%
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
(1)
Frequency
155.52 MHz
156.25 MHz
155.52 MHz
156.25 MHz
BREFCLK
212.5 MHz
312.5 MHz
212.5 MHz
312.5 MHz
for more information on calculating latency.
2.488
Min
45
45
RJ
specified is peak-to-peak, estimated at
0.15
0.14
0.39
0.42
0.03
0.03
0.14
0.17
0.12
0.12
0.25
0.25
Typ
60
60
14
50
50
Max
6.25
0.20
0.19
0.48
0.54
0.17
0.17
0.26
0.35
0.18
0.20
0.39
0.39
19
55
55
Module 3 of 4
TXUSR
cycles
Units
Gb/s
CLK
UI
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
%
%
(2)
17

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