XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 89

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Table 27: RocketIO Transmitter Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
5.
Serial data rate, full-speed clock
Serial data rate, half-speed clock
(2X oversampling)
Serial data output deterministic jitter
Serial data output random jitter
TX rise time
TX fall time
Transmit latency
TXUSRCLK duty cycle
TXUSRCLK2 duty cycle
Serial data rate in the -5 speed grade is limited to 2.0 Gb/s in both wirebond and flipchip packages.
UI = Unit Interval
For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in
receive jitter tolerance specifications defined in this data sheet.
The oversampling techniques described in
Transmit latency delay TXDATA to TXP/TXN. Refer to
TXDATA[16:0]
TXUSRCLK2
R
TXP/TXN
Description
(5)
0
1
DATA ORIGINATES
Figure 5: RocketIO Transmit Latency (Maximum, Including CRC)
2
(3)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
. . . . .
XAPP572
Symbol
T
T
T
F
T
T
TX2DC
20
TXLAT
T
T
TXDC
GTX
RTX
FTX
DJ
RJ
are required to meet these specifications for serial rates less than 1 Gb/s.
RocketIO Transceiver User Guide
1
21 22
www.xilinx.com
1.0626 Gb/s – 2.125 Gb/s
1.0626 Gb/s – 2.125 Gb/s
2.126 Gb/s – 3.125 Gb/s
2.126 Gb/s – 3.125 Gb/s
1.0 Gb/s – 1.0625 Gb/s
1.0 Gb/s – 1.0625 Gb/s
600 Mb/s – 999 Mb/s
600 Mb/s – 999 Mb/s
Wirebond packages
Wirebond packages
T
. . . . .
Flipchip packages
Flipchip packages
TXLAT
Excluding CRC
Including CRC
Conditions
20% – 80%
320
16
321 322
XAPP572
for more information on calculating latency.
are required to meet the transmit jitter and
. . . . .
0.600
0.600
Min
1.0
1.0
45
45
340 341 342
Typ
120
120
14
50
50
8
17
DATA ARRIVES
DS083-3_03_082301
3.125
2.5
Max
0.08
0.18
0.17
0.08
0.05
0.18
0.19
0.18
1.0
1.0
17
11
55
55
. . . .
(1)
(1)
(4)
(4)
Module 3 of 4
TXUSR
cycles
Units
Gb/s
Gb/s
Gb/s
Gb/s
CLK
UI
UI
ps
ps
UI
UI
UI
UI
UI
UI
%
%
(2)
18

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