XC2VP7-5FG456I Xilinx Inc, XC2VP7-5FG456I Datasheet - Page 5

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XC2VP7-5FG456I

Manufacturer Part Number
XC2VP7-5FG456I
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FG456I

Package
456FBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
248
Ram Bits
811008
Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
248
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Each RocketIO or RocketIO X core implements the following
technology:
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
1. Refer to
2. Refer to
3. Refer to
DS083 (v4.7) November 5, 2007
Product Specification
Serializer and deserializer (SERDES)
Monolithic clock synthesis and clock recovery (CDR)
10 Gigabit Attachment Unit Interface (XAUI) Fibre
Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express,
Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48
compatibility
8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X)
selectable FPGA interface
8B/10B (RocketIO) or 8B/10B and 64B/66B
(RocketIO X) encoder and decoder with bypassing
option on each channel
Channel bonding support (two to twenty channels)
-
Receiver clock recovery tolerance of up to
75 non-transitioning bits
50Ω (RocketIO X) or 50Ω /75Ω selectable (RocketIO)
on-chip transmit and receive terminations
Programmable comma detection and word alignment
Rate matching via insertion/deletion characters
Automatic lock-to-reference function
Programmable pre-emphasis support
Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
Optional transmit and receive data inversion
Cyclic Redundancy Check support (RocketIO only)
PowerPC RISC CPU
-
-
-
-
-
-
-
-
Storage Control
Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
Thirty-two 32-bit general purpose registers (GPRs)
Static branch prediction
Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
Enhanced string and multiple-word handling
Big/little endian operation support
Table 4, Module 2
XAPP659
XAPP653
R
(1)
for more information.
for more information.
for detailed information about RocketIO and RocketIO X transceiver compatible protocols.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
www.xilinx.com
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
-
-
-
-
-
-
Virtual mode memory management unit (MMU)
-
-
-
OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
PowerPC timer facilities
-
-
-
-
Debug Support
-
-
-
-
-
-
-
Two hardware interrupt levels support
Advanced power management support
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
Bidirectional block (any combination of input and output
configurations)
LVTTL, LVCMOS (3.3V,
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
GTL and GTLP
Separate instruction and data cache units, both
two-way set-associative and non-blocking
Eight words (32 bytes) per cache line
16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
Operand forwarding during instruction cache line fill
Copy-back or write-through DCU strategy
Doubleword instruction fetch from cache improves
branch latency
Translation of the 4 GB logical address space into
physical addresses
Software control of page replacement strategy
Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
64-bit time base
Programmable interval timer (PIT)
Fixed interval timer (FIT)
Watchdog timer (WDT)
Internal debug mode
External debug mode
Debug Wait mode
Real Time Trace debug mode
Enhanced debug support with logical operators
Instruction trace and trace-back support
Forward or backward trace
(2)
2.5V, 1.8V, and 1.5V)
Module 1 of 4
(3)
(3)
4

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