XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 53

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
T
Maximum Frequency
F
T
Maximum Frequency
F
BCCCK_CE
BCCCK_S
BCCKO_O
MAX
BUFIOCKO_O
MAX
T
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
T
BCCCK_CE
BGCKO_O
/T
(2)
Symbol
Symbol
/T
BCCKC_S
BCCKC_CE
(BUFG delay from I0 to O) values are the same as T
and T
(1)
BCCKC_CE
(1)
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from
I0/I1 to O
Global clock tree (BUFG)
Clock to out delay from I to O
I/O clock tree (BUFIO)
Description
Description
www.xilinx.com
All
All
LX20T
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX70T,
FX100T, and FX130T
FX30T
LX155 and LX155T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
LX20T
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, and
FX70T
LX155, LX155T, and FX100T
FX130T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
BCCKO_O
Devices
values.
1.08
0.27
0.00
0.27
0.00
0.19
0.23
0.12
710
N/A
N/A
N/A
710
650
550
N/A
-3
-3
Speed Grade
Speed Grade
1.16
0.27
0.00
0.27
0.00
0.24
0.22
0.23
0.14
0.22
710
667
667
600
500
500
-2
-2
1.29
0.31
0.00
0.31
0.00
0.30
0.25
0.25
0.30
0.25
644
600
600
550
450
450
-1
-1
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
53