XC6SLX25T-3FGG484C Xilinx Inc, XC6SLX25T-3FGG484C Datasheet - Page 52
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XC6SLX25T-3FGG484C
Manufacturer Part Number
XC6SLX25T-3FGG484C
Description
FPGA Spartan®-6 Family 24051 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Specifications of XC6SLX25T-3FGG484C
Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
24051
Device Logic Units
15000
Number Of Registers
30064
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
958464
Number Of Logic Elements/cells
24051
Number Of Labs/clbs
1879
Total Ram Bits
958464
Number Of I /o
250
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX25T-3FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)
Table 53: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
4.
LOCK_DLL
Delay Lines
DCM_DELAY_STEP
Input Frequency Ranges
CLKIN_FREQ_FX
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input,
CLKIN_PER_JITT_FX
The values in this table are based on the operating conditions described in
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of
±(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns
or 100 ps, the maximum jitter is ±(100 ps + 150 ps) = ±250 ps.
A typical delay step size is 23 ps.
DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180).
When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as
it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the F
BUFIO2 limits).
CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.
Symbol
Symbol
(3)
(5)
(2)
Frequency for the CLKIN input. Also
described as F
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency:
FCLKFX < 150 MHz.
based on CLKFX output frequency:
FCLKFX > 150 MHz.
Period jitter at the CLKIN input.
(4)
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
5 MHz < CLKIN_FREQ_DLL
< 50 MHz.
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
CLKIN_FREQ_DLL > 50 MHz
Finest delay resolution, averaged
over all steps.
Description
CLKIN
Description
.
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Min
Table 2
10
–
–
Min
0.5
–
–
–
-3
-3
Max
and
0.60
375
40
±300
±150
Max
5
±1
(1)
Table
(3)
(Cont’d)
Min
10
Min
–
–
51.
0.5
–
–
–
-3N
-3N
Speed Grade
Speed Grade
Max
0.60
375
±300
±150
Max
40
MAX
5
±1
(3)
(see
Min
Min
10
0.5
–
–
Table 47
–
–
–
-2
-2
333
±300
±150
Max
0.60
Max
(1)
40
±1
5
and
(3)
Table
Table 48
Min
Min
0.5
10
–
–
–
–
–
51.
-1L
-1L
200
±300
±150
Max
for BUFG and
Max
0.60
±1
40
5
(3)
Units
MHz
Units
ps
ps
ns
ms
ms
ps
52