XCV50E-6PQ240C Xilinx Inc, XCV50E-6PQ240C Datasheet - Page 58

• Manufacturer Part Number: XCV50E-6PQ240C
• Description: FPGA Virtex™-E Family 20.736K Gates 1728 Cells 357MHz 0.18um (CMOS) Technology 1.8V 240-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240C

• Package: 240PQFP
• Family Name: Virtex™-E
• Device Logic Gates: 20736
• Device Logic Units: 1728
• Device System Gates: 71693
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 158
• Ram Bits: 65536
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 44: Bidirectional I/O Library Macros
Revision History
The following table shows the revision history for this document.
Module 2 of 4
52
IOBUFDS_FD_LVDS
IOBUFDS_FDE_LVDS
IOBUFDS_FDC_LVDS
IOBUFDS_FDCE_LVDS
IOBUFDS_FDP_LVDS
IOBUFDS_FDPE_LVDS
IOBUFDS_FDR_LVDS
IOBUFDS_FDRE_LVDS
IOBUFDS_FDS_LVDS
IOBUFDS_FDSE_LVDS
IOBUFDS_LD_LVDS
IOBUFDS_LDE_LVDS
IOBUFDS_LDC_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
12/7/99
1/10/00
1/28/00
2/29/00
5/23/00
7/10/00
8/1/00
Date
Version
Name
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Initial Xilinx release.
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
Updated pinout tables, V
Correction to table on p. 22.
•
•
•
•
•
Numerous minor edits.
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
D, T, GE, G, CLR
D, T, GE, G, PRE
D, T, CE, C, CLR
D, T, CE, C, PRE
www.xilinx.com
D, T, CE, C, R
D, T, CE, C, S
D, T, C, PRE
D, T, G, CLR
D, T, G, PRE
D, T, C, CLR
D, T, GE, G
D, T, CE, C
CC
D, T, C, R
D, T, C, S
Inputs
D, T, C
D, T, G
page 20, and corrected Figure 20.
BYP
values, buffered Hex Line info, p. 8, I/O Timing
Revision
Bidirectional
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
Production Product Specification
DS022-2 (v2.8) January 16, 2006
Outputs
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
R