CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 106

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-66. Asynchronous Read Cycle Specifications
Table 11-67. Asynchronous Write Cycle Specifications
Document Number: 001-11729 Rev. *R
Note
T
Tcel
Taddrv
Taddrh
Toel
Tdoesu
Tdoeh
T
Tcel
Taddrv
Taddrh
Twel
Tdcev
Tdweh
46. Limited by GPIO output frequency, see
Parameter
Parameter
EM_ WEn
EM_ Data
EM_ CEn
EM_ OEn
EM_ Addr
EMIF clock period
EM_CEn low time
EM_CEn low to EM_Addr valid
Address hold time after EM_WEn high
EM_WEn low time
EM_CEn low to data valid
Data hold time after EM_WEn high
EMIF clock period
EM_CEn low time
EM_CEn low to EM_Addr valid
Address hold time after EM_Wen high
EM_OEn low time
Data to EM_OEn high setup time
Data hold time after EM_OEn high
Taddrv
Table 11-10
Tdcev
Description
Description
[46]
[46]
Figure 11-68. Asynchronous Write Cycle Timing
on page 74.
Tcel
Twel
Address
Vdda ≥ 3.3 V
Vdda ≥ 3.3 V
Conditions
Data
Conditions
Taddrh
Tdweh
PSoC
2T – 5
2T – 5
T + 15
30.3
Min
T – 5
T – 5
30.3
–
T
3
Min
–
T
–
T
®
3: CY8C38 Family
Typ
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2T + 5
2T+ 5
T + 5
T + 5
Max
Data Sheet
Max
–
5
–
–
–
–
5
–
7
–
Page 106 of 129
Units
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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