CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 27

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1 percent at 3 MHz, up to ±7 percent at
62 MHz. The IMO, in conjunction with the PLL, allows generation
of CPU and system clocks up to the device's maximum
frequency (see PLL). The IMO provides clock outputs at 3, 6, 12,
24, 48, and 62 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.1.1.3 PLL
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a trade off between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 67 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
Document Number: 001-11729 Rev. *R
7
12-48 MHz
3-62 MHz
Doubler
IMO
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
4-25 MHz
ECO
24-67 MHz
PLL
Figure 6-1. Clocking Subsystem
External IO
0-66 MHz
or DSI
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
System
32 kHz ECO
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz. The 1-kHz clock (CLK1K) is typically used for a
background ‘heartbeat’ timer. This clock inherently lends itself to
low-power supervisory operations such as the watchdog timer
and long sleep intervals using the central timewheel (CTW).
The central timewheel is a 1-kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
The 100-kHz clock (CLK100K) works as a low-power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel. The fast timewheel
is a 100-kHz, 5-bit counter clocked by the ILO that can also be
used to wake the system. The fast timewheel settings are
programmable, and the counter automatically resets when the
terminal count is reached. This enables flexible, periodic
wakeups of the CPU at a higher rate than is allowed using the
central timewheel. The fast timewheel can generate an optional
interrupt each time the terminal count is reached.
1,33,100 kHz
ILO
7
PSoC
CPU Clock Divider
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
4 bit
16 bit
®
3: CY8C38 Family
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Clock
CPU
Clock
Bus
Data Sheet
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